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Hi I'm new in quartus II.
I would just like to ask on how to implement 2-digit Adder / Subractor HEX3 = +/- SW[7:0] = BCD PB[0] = + PB[1] = - PB[2] = = PB[3] = reset we are using a hardware called Cyclone II. I have tried a code but it does not finish compiling. I don't know why. Can someone help me?Link Copied
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You must write HDL (Hardware Description Language) code, not programming code.
What you describe in your code is supposed to be synthesized into logic gates, not to be executed by a processor. I think your present code is useless and it needs to be completely rewritten. A few hints: - those while loops make no sense. Remember: this is HDL, not software - the hex to bcd decoders could be more conveniently fitted into a reusable submodule - use a clock to sync the whole process - take a basic HDL course or read a Verilog tutorial
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