Hello,
I have been trying to simulate my simple design which consists of
> NIOS II Embedded Processor
> DDR3 SDRAM controller with ALTMEMPHY
> Systems ID peripheral
> JTAG UART Peripheral.
according to tutorials i have generated the VHDL models and have written a very simple application which writes and reads data from DDR3. I have stored my application in the external memory. But during simulation i am getting errors in the questasim console "ERROR: <testbench module name> /<signal name> is 'X'.
I went through the testbench that was generated through Qsys and understood that i need to Initialize the memory.But i dont know how???.We can enter the file name in the testbench.But i am not sure which file contains the data for initialization of the signals.
How can i generate a .Hex file for the DDR memory (similar to when working with onchip memory).
(NOTE: This application has worked when i used an onchip m/m to store it and used the DDR3 jsut to read and write data).
It seems that there is very less information about External Memory simulation.
There is an option to include the Mem_init file in line number 89,90 and 204,205 (testbench attached with this post),but sadly NIOS II does not create any .hex file for external memories.
PLEASE HELP!!!!
