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altera_pll + altlvds_rx = problems with fitting

Altera_Forum
Honored Contributor II
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Hello forum, i wanna create a lvds reciever with deserializer logic, iam using Cyclone 5 E (5cefa7f31i7n). 

I try to create 1 pll in 5B bank (lvds mode with 8 clkouts), and 4 altlvds_rx, in between them i paste cyclonev_pll_lvds_output, because i recived errors with pll_loaden and pll_lvdsclk, this error is disapear but fitter don't want to fit project. 

Error (14996): The Fitter failed to find a legal placement for all periphery components Info (14987): The following components had the most difficulty being legally placed: Info (175029): PLL LVDS output LVDS_clock_buffer_inst3 (67%) Info (175029): PLL LVDS output LVDS_clock_buffer_inst2 (33%) Error (14986): After placing as many components as possible, the following errors remain: Error (175001): Could not place PLL LVDS output Info (14596): Information about the failing component: Info (175028): The PLL LVDS output name: LVDS_clock_buffer_inst2 Info (175013): The PLL LVDS output is constrained to the region (89, 1) to (89, 2) due to related logic Info (175015): The I/O pad CMV_DATA_IN is constrained to the location PIN_T28 due to: User Location Constraints (PIN_T28) Info (14709): The constrained I/O pad is driven by this PLL LVDS output Error (11238): Node is not compatible with other nodes placed at the same location either because there are too few available PLL LVDS output locations, or the nodes have different inputs, parameters, or both. Error (11239): Could not merge with previously placed PLL LVDS outputs at location PLLLVDSOUTPUT_X89_Y1_N2 Info (11237): Already placed at this location: PLL LVDS output LVDS_clock_buffer_inst1 Info (175013): The PLL LVDS output is constrained to the region (89, 1) to (89, 2) due to related logic Info (175015): The I/O pad CMV_DATA_IN is constrained to the location PIN_V26 due to: User Location Constraints (PIN_V26) Info (14709): The constrained I/O pad is driven by this PLL LVDS output Error (11239): Could not merge with previously placed PLL LVDS outputs at location PLLLVDSOUTPUT_X89_Y2_N2 Info (11237): Already placed at this location: PLL LVDS output LVDS_clock_buffer_inst0 Info (175013): The PLL LVDS output is constrained to the region (89, 1) to (89, 2) due to related logic Info (175015): The I/O pad CMV_DATA_IN is constrained to the location PIN_T25 due to: User Location Constraints (PIN_T25) Info (14709): The constrained I/O pad is driven by this PLL LVDS output Error (175001): Could not place PLL LVDS output Info (14596): Information about the failing component: Info (175028): The PLL LVDS output name: LVDS_clock_buffer_inst3 Info (175013): The PLL LVDS output is constrained to the region (89, 1) to (89, 2) due to related logic Info (175015): The I/O pad CMV_DATA_IN is constrained to the location PIN_U27 due to: User Location Constraints (PIN_U27) Info (14709): The constrained I/O pad is driven by this PLL LVDS output Error (11238): Node is not compatible with other nodes placed at the same location either because there are too few available PLL LVDS output locations, or the nodes have different inputs, parameters, or both. Error (11239): Could not merge with previously placed PLL LVDS outputs at location PLLLVDSOUTPUT_X89_Y1_N2 Info (11237): Already placed at this location: PLL LVDS output LVDS_clock_buffer_inst1 Info (175013): The PLL LVDS output is constrained to the region (89, 1) to (89, 2) due to related logic Info (175015): The I/O pad CMV_DATA_IN is constrained to the location PIN_V26 due to: User Location Constraints (PIN_V26) Info (14709): The constrained I/O pad is driven by this PLL LVDS output Error (11239): Could not merge with previously placed PLL LVDS outputs at location PLLLVDSOUTPUT_X89_Y2_N2 Info (11237): Already placed at this location: PLL LVDS output LVDS_clock_buffer_inst0 Info (175013): The PLL LVDS output is constrained to the region (89, 1) to (89, 2) due to related logic Info (175015): The I/O pad CMV_DATA_IN is constrained to the location PIN_T25 due to: User Location Constraints (PIN_T25) Info (14709): The constrained I/O pad is driven by this PLL LVDS output Error (14996): The Fitter failed to find a legal placement for all periphery components Info (14987): The following components had the most difficulty being legally placed:  

i don't understand this errors, why they appear ? 

Did cyclone V have some restrictions about lvds_rx on bank ? or its problem with LVDS_clock_buffer?
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Altera_Forum
Honored Contributor II
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I am not that familiar with the CV devices, but ArriaV uses dedicated clock structures for LVDS RX clocking. There are some restrictions that say that multiple clocks cannot be interleaved on a single bank. Check you device datasheet for details.

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Altera_Forum
Honored Contributor II
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Remove all the pin assignments and let it autofit.  

If it can fit, see if it is as supernode mentioned OR if you are following the placement rule as certain PLL only supports one edge but not across edge. Example: Right corner PLL support LVDS on Right edge. 

If it still cannot fit, i think most probably it is due to the PLL cannot support as many channels on that particular edge.
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Altera_Forum
Honored Contributor II
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Hello,have you solved this problem? i miss the same problem too.http://www.alteraforum.com/forum/attachment.php?attachmentid=11867&stc=1

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