Hi, i'm writing a vhdl code to drive the UART RS232 module implemented on Qsys. My EVB have a 50MHz clock. The same clock drive the SoC and my logic. I wrote a dummy FSM to read the status register of the UART IP but the response il always x0000.
Attached the Qsys system and the timing dagram of my code.
P.S. the CS is always high
