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Hi guys!
Im newbie. Just wrote simple code D-trigger by verilog.module dff_m(
input clk, output reg q,
input d, output n_q,
input reset
);
always @(posedge clk)
begin
if(reset)
q <= 1'b0;
else
q <= d;
end
endmodule
And a test-bench module dff_m_tb;
reg clk;
reg d;
reg reset;
wire q;
wire n_q;
dff_m uut(
.clk(clk),
.d(d),
.reset(reset),
.q(q),
.n_q(n_q)
);
initial
begin
clk=1;
while(1)
# 10 clk=~clk;
end
initial
begin
d=0;reset=0;
# 40;d=1;
# 20;d=0;
# 40;d=1;
# 20;d=0;
end
endmodule
Simulation shows http://www.alteraforum.com/forum/attachment.php?attachmentid=10202&stc=1 Question : why there isnt delay between output q and input d. As i know d-trigger is a delay - flip-flop. Best regards.
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