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Quartus 12. --Analysis and Synthesis Failed- Help Needed

Altera_Forum
Honored Contributor II
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Hello here is a small program that I wrote in VHDL(please see attachment). Synthesis fails in Quartus with the following error. 

Error[10028]: can't resolve multiple constant drivers for net wr_data[]... 

Can someone help me with solve it? 

 

Thanks. 

Manoj
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Altera_Forum
Honored Contributor II
533 Views

 

--- Quote Start ---  

Hello here is a small program that I wrote in VHDL(please see attachment). Synthesis fails in Quartus with the following error. 

Error[10028]: can't resolve multiple constant drivers for net wr_data[]... 

Can someone help me with solve it? 

 

Thanks. 

Manoj 

--- Quote End ---  

 

 

It is telling you you have assigned to write_data in two assignments (the combinatorial logic before stste machine then inside state machine).  

Which one you want?
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Altera_Forum
Honored Contributor II
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Thanks Kaz, for your reply. I would like to assign both the assignments, as I need it for my logic. 

Any idea how to implement it? 

 

Thanks, 

Manoj
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Altera_Forum
Honored Contributor II
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you should assign to wr_data in one construct but check priority. 

 

wr_data <= x"00" when state = s1 else x"00" when count_reg = x"00" else x"01" when count_reg = x"01" else x"02" when count_reg = x"02" else x"03" when count_reg = x"03" else x"04" when count_reg = x"04" else x"05" when count_reg = x"05" else x"06" when count_reg = x"06" else x"07" when count_reg = x"07" else x"08" when count_reg = x"08" else x"09" when count_reg = x"09" else x"0A" when count_reg = x"0A" else x"FF";
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Altera_Forum
Honored Contributor II
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Thanks so much Kaz. It works now!. 

 

Regards, 

Manoj
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