Problem simulating transceiver megacore Nativelink

[Altera_Forum]

I am new to Altera Megacores and am having trouble simulating a VHDL project using Altera Megacores in the web edition of Quartus/ Modelsim-Altera. I am trying to use Nativelink so I do not have to get involved with the details of the MegaCore files and libraries for the moment. 

 I am using Quartus II 64 Bit Version 14.1.0. Build 12/03/2014 SJ Web Edition.  I have connected a Cyclone V Transceiver Native PHY, Transceiver PHY Reset Controller and Transceiver Reconfiguration controller produced from the IP Catalogue together in a schematic then generated an HDL file from the schematic.  I set up the simulation tab in "Settings/EDA Tool Settings" to compile a test bench generated from a template using Quartus.  The design compiles without error but when I run RTL simulation from Quartus the test bench is not bound to the components it uses so all of their signals are undefined.  I realise I am probably making some silly error and would be very grateful for any help.  I attach the archived project.  Resolved - changed the EDA netlist setting from VHDL to Verilog HDL and it seems to be working now.

[Altera_Forum]

Hello, I just did a small design with the Cyclone V Transceiver Native IP Core. Please take a look at my attachments. I archived my project open it up and look at my .bdf file to see how I connected up the transceiver, the reset module and the configuration module. In an not using any protocol. I'm only use the Gbe Protocol-Ordered Sets and Special code (IDL1 and Carrier Extend) to implement a simple link to another transceiver on another board, see page 4-17 in the Cyclone V Device Handbook Volume 2. I'm also using the tx_datak[] and rx_datak[] port to put the link in Control mode or Data mode. Please take a look at my testbench in the testbench directory. I only did an Function Simulation because the RTL simulation would not work. In my attached design I use a testbench to send data to the transceiver and in the testbench I connect the rx_serial_data port to the tx_serial_data port. I first send and IDLE code then a Carrier Code and then real data.  

 Hope this helps. I spent a long time trying to figure out the Transceivers.   joe

[Altera_Forum]

Thanks very much for your reply Joe. 

 I found my problem was due to choosing VHDL for the output EDA netlist setting in Quartus Nativelink set up. When I set to Verilog HDL it all works fine. At least it simulates. Now I have to make it work.  I only just started looking at transceivers and it is the first time I have used the MegaCores. I wasn't sure if the problems I was having were due to my design or with the tools.  I will have a look through your archive and learn from your hard work.  Thanks again.  Phil

[Altera_Forum]

You bet. I have another example where I simply write to a 16-bit fifo a state machine then reads that fifo and write it to the transceiver block. When the Transceiver block receives data I have a state machine to save the received data to a 16-bit fifo and also set a flag indicating data has been received. A nice simple interface that anyone can use, simply write to a tx fifo, set a big high to transmit the data, and on the receive site, monitor a receive interrupt indicating data has arrived.  

 If you are interested I can send upload it.   joe

[Altera_Forum]

Thanks for the offer Joe, sounds like a very neat solution. You have been more than helpful and I don't want to waste any more of your time.  

 I am doing a camera design that just transmits a continuous stream of bits captured from a sensor so no receive or handshaking is involved. I am aiming to use the Altera SDI core to do all of the hard work with the transceivers. It has a defined interface so I just need to understand how to drive my sensor to make it comply with this at the moment.  Regards  Phil