DE2-115 (Help w/ LED & SWITCH program)

Altera_Forum · ‎03-06-2015

Hello, I'm having trouble understanding a few parameters of my ENTITY statement that seem to play a big role in whether the program executes correctly on my DE2-115 board. This is part of Lab1_Part1 in the SystemsCD I received with my device. The same lab is located here ftp://ftp.altera.com/up/pub/altera_material/12.0/laboratory_exercises/digital_logic/de2/vhdl/lab1_vhdl.pdf . Its only part 1 which is on page 1 and 2. It simply links all 18 Red LED's to all 18 Toggle Switches. So by toggling a switch turned its corresponding LED on and vice versa.

when i first wrote this code and uploaded it to my board it didn't work. it compiled fine but it did not execute on the hardware correctly.

I tried doing what they suggested which is import the "DE2-115_pin_assignments" file. I did this through the import assignments button under Assignments in Quartus II. I couldn't find the .csv file that they wanted so I created a .txt file instead and imported that. After uploading the code it automatically turned on two LEDs but that was it and toggling the switches did nothing. I'm attaching the file that I imported as my assignment file just for completeness of this thread. Its titled "DE2-115_pin_assignments.txt".

i troubleshooted this by going through the whole pin assignment process manually

I typed in each port assignment location for each input "that being each switch" and for each output "that being each LED". Uploaded it for the second time and got the exact same results as before.

here is my code that was not executing correctly on my board

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY lab1_part1 IS
PORT ( SIGNAL SW: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
       SIGNAL LEDR: OUT STD_LOGIC_VECTOR(17 DOWNTO 0));       
END lab1_part1;
ARCHITECTURE behavior OF lab1_part1 IS
BEGIN
LEDR <= SW;
END behavior;

further troubleshooting

The next step I took in troubleshooting this was changing up the ENTITY statement. I declared my two object names "SW and LEDR" as SIGNAL objects. So I erased the "SIGNAL" declaration for each object name and uploaded the new code to my board. It WORKED!!

Here is what my new code looks like

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY lab1_part1 IS
PORT ( SW: IN STD_LOGIC_VECTOR(17 DOWNTO 0); --must not use SIGNAL for some reason
	   LEDR: OUT STD_LOGIC_VECTOR(17 DOWNTO 0)); --must not use SIGNAL for some reason	   
END lab1_part1;
ARCHITECTURE behavior OF lab1_part1 IS
BEGIN
LEDR <= SW;
END behavior;

so my question is

Why don't I declare my object names as a object type "SIGNAL"? According to the definition of SIGNAL it serves as passing values in and out of the circuit as well as between its internal units. Thought that was what SW and LEDR are?!

I looked at the pin_assignment.txt file I imported in as the assignment file thinking that I may find SW and LEDR declared as something different but it doesn't indicate that. It just shows the location assignment for a pin. So really confused on why it worked when I took out SIGNAL and why it didn't work when I had SIGNAL in there. Could someone explain what is going on?

Altera_Forum · ‎03-07-2015

The pin assignments csv file is on the CD in the DE2_115_lab_exercises folder. It isn't in the folders for the individual exercises.

.

Altera_Forum · ‎03-07-2015

Thanks I found the csv file. I was more curious on why my code wasn't behaving as I wanted it to. Could you explain why I shouldn't be using SIGNAL as an object definition for SW and LEDR?

Altera_Forum · ‎03-07-2015

I don't know why signal wouldn't work. I can only say that I haven't seen it used in the VHDL examples I've looked at.