Cost of implementation of logic and arithmetic operations

Altera_Forum · ‎03-11-2015

Hello Members,

My question:

What is the cost of implementation, in terms of logic elements, frequency, memories, area ..., of the logic and arithmetic operations (addition, subtraction, multiplication, division ...) in fpga cyclone ii?

for example, to implement a multiplier 2*2 bits, how much we need:

+ Logic elements

+ memory

+ Frequency

+ area

+...

Regards,

Altera_Forum · ‎03-12-2015

You can find that out easily by creating and compiling a simple verilog or vhdl with the circuit you are interested in. Quartus produces comprehensive reports of resource usage on a particular FPGA family when you compile.

Altera_Forum · ‎03-12-2015

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You can find that out easily by creating and compiling a simple verilog or vhdl with the circuit you are interested in. Quartus produces comprehensive reports of resource usage on a particular FPGA family when you compile.

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Thank you Galfonz for your answer, effectively, we can have the cost of implementation of circuits using the report provides in quartus, but i want the cost of basic arithmetic and logical operators before starting the coding because I want to use these settings elsewhere. I searched into the datasheet of altera but I only found one example of the multiplier 19*19 bits

Altera_Forum · ‎03-13-2015

I should have mentioned specifically in my reply that I don't know of any such documentation. I don't know if a given operation will always take the same resources. It might depend on the context and on what timing constraints you've entered. I know I've seen resource usage change significantly by what look like small changes to code and/or timing constraints.

Altera_Forum · ‎03-13-2015

There is no such data available, because the synthesisor can do lots of work to minimise logic usage depending on your design. Also, the device family has a large effect on resource usage depending on whether it uses 4/6 input LUTs.

So there is no such thing as logic usage for a basic block.

Altera_Forum · ‎05-14-2015

Hi,

Yah I agree to Galfonz.

The best way to figure this out is to write a sample code and synthesize it. Because the number of logic elements will differ for different devices and timing constraints.

Thanks,