Backbone,timing,BLVDS and max speed

[Altera_Forum]

Hi all! 

 Iam solving one problem and i need the advice.  Iam working on device where will eurocards and this will be hot-swapable. So because of the max frequency od DIN41612 is 557MHz i will sync the bus with frequency of clock about 50 MHz, then i will use pll to double the frequency (because of synchro of BLVDS transceivers). So i will use 16 BLVDS (on cyclone 4 in LQFP144 package) to deliver signal on bus. The FPGA will something like multiplexer and bridge together. Maximum supposed frequency will be about 350 MHz but standard will be 100/50 MHz.   So my question is,  Will be able the Cyclone IV comunicate over BLVDS with frequency 350 MHz? Will be able the core works on frequency 350 MHz? Will be able to communicate with 6 eurocards in DIN41612 if there is 10 inch lenght on backplane?

[Altera_Forum]

Anyone can help?

[Altera_Forum]

Hi Marko5211, 

 Regarding your inquiry "Will be able to communicate with 6 eurocards in DIN41612 if there is 10 inch lenght on backplane?", I think it is recommended to perform signal integrity simulation with IBIS model or Hspice model to evaluate if the input and output specs of CIV and eurocards are met. If specs are violated, then it is unlikely that the interface will work.  You can find the IBIS model at https://www.altera.com/support/support-resources/download/board-layout-test/ibis/ibs-ibis_index.html and HSPICE model at https://www.altera.com/support/support-resources/download/board-layout-test/hspice.html

[Altera_Forum]

"Will be able the core works on frequency 350 MHz?" 

 Regarding the above question, you could refer to the core performance specs in the CIV device datasheet -> Table 1–24. Clock Tree Performance for Cyclone IV Devices, look for your specific part to check if the clock tree can meet your target 350MHz. If can, the next you would need to do is to perform timing analysis with your design to see if there is any timing violation. Note that the specs state the max limit but the core operating max frequency will be limiting by your design as well. Since you are using PLL in your design, you might want to check also Table 1–25. PLL Specifications for Cyclone IV Devices to check the PLL frequency. Hope these help.

[Altera_Forum]

"Will be able the Cyclone IV comunicate over BLVDS with frequency 350 MHz?" 

 You might want to first perform signal integrity simulation with IBIS/Hspice models to see if can meet the IO specs. Then run through QII timing analyzer to see if the fmax can meet your target.