Question about building a prbs generator, using a lfsr, schematic entry

[Altera_Forum]

Hi, 

 I want to generate a random bit sequence, using a schematic entry in quartus. For example and to test, i tried a 4bit prbs. (see the screenshot attached)  I used a LFSR, built it with D Latches and XOR Gates. The Problem is, i have to set an initial seed. So I used an input pin to feed PRN and an other to feed CLRN. In my testbench, I defined the values of those input pins. But as far as i can see, the D latch is initialized each clock step.   Is it right, that i have to switch off (or cut off) the initialization pin to let the d latch work in normal mode?   Btw. are there other possibilities to generate a prbs via schematic entry?  Thank you in advance.  regards   EDIT: When i define all PRN and CLRN ports of the d latches, modelsim reports an error: Error: (vsim-3601) Iteration limit reached at time..... I also tried to enlarge the iteration time value, but the error still occurs.

[Altera_Forum]

I recommend learning an HDL language rather than using schematic entry. 

 Here's an LFSR/PRBS tutorial. Look at the matrix math in the document and its corresponding implementation in HDL. There's no way you can do that with schematic entry.  https://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf https://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip  Cheers, Dave

[Altera_Forum]

Thank you Dave, 

 I already visited this links to get some information.  Is it possible to generate a block or an IP, using VHDL code? So i could use the generated block in the schematic.  regards

[Altera_Forum]

--- Quote Start ---   Is it possible to generate a block or an IP, using VHDL code? So i could use the generated block in the schematic.   --- Quote End ---   Yes, you can create symbols for HDL code.   I don't use schematics, so you'll have to read through the Quartus documentation to see how to generate a symbol and how to access and set the generics on a symbol.  You would be much better served using an HDL directly. You cannot simulate schematics, without first translating them to an HDL and you cannot take your schematic design and use it in another vendors tools. HDL is much more flexible.  Cheers, Dave

[Altera_Forum]

Thank you again Dave, 

I know, that it would be better to use HDL. Before Quartus, i worked a lot with simulink, so the schematic entry is the thing i want to start in quartus.  Now, i created a prbs block. Works as it should so far.  Thank you for your support!  regards

[Altera_Forum]

--- Quote Start ---   I know, that it would be better to use HDL. Before Quartus, i worked a lot with simulink, so the schematic entry is the thing i want to start in quartus.   --- Quote End ---   Ok, I just wanted to provide you some advice. Its ok for you to ignore it :)    --- Quote Start ---   Now, i created a prbs block. Works as it should so far.  Thank you for your support!   --- Quote End ---   Great! You're welcome.  Cheers, Dave