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How did you fix it?
I'm getting the same error on my De1-Soc board and can't figure out how to fix it.- Mark as New
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It just maybe your design is too big for the FPGA. One other solution is to try and recompile with the --high-effort flag and see.
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You can see the source usage estimation in the acl_quartus_report.txt file 。you can also refer to the log file under the project file folder bin_nameofkernel.
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