library use clause errors

Altera_Forum · ‎05-06-2015

I am using Altera version 13.0.0.

The compiler is complaining about this code:

library ieee;

use ieee.std_logic_1164.all;

library basicblocks;

use basicblocks.d_flipflop.all;

use basicblocks.inverter.all;

entity ...

with errors

VHDL Use Clause error at tps2834.vhdl(5): design library "basicblocks" does not contain primary unit "d_flipflop"

VHDL error at tps2834.vhdl(5): selected name in use clause is not an expanded name

Under Assignments|Settings|Libraries, I have placed a directory

c:\hdl\libraries\basicblocks

in the global libraries section. This directory contains a file

d_flipflop.vhdl

which contains the required entity d_flipflop.

I am getting similar errors for the inverter clause as well. I had a bunch of small functions in a file basicblocks.vhdl, but that failed with the same errors.

What am I doing wrong?

Altera_Forum · ‎05-07-2015

the .all reference needs to be attached to a package. If the thing you are refering to is an entity, you dont need to call use on it at all if you dont want to, you can just use direct instantiation.


library basicblocks;
--no use cases required
--instatitate a d_flipflop
d_inst : entity basicblocks.d_flipflop
generic map (
  --etc
)
port map (
  -- etc
);

Altera_Forum · ‎05-07-2015

Quartus global libraries are not the same thing as VHDL libraries. It's just a location for Quartus to look for files that haven't been manually added to the project.

Go to Assignments -> Files -> Add Files and add d_flipflop.vhdl. After adding, click on Properties and set the library to basicblocks. Now it will be compiled into that library(otherwise everything goes into work).

Altera_Forum · ‎05-15-2015

@tricky:

I am still getting use clause errors. The error below appears if I have a files named basicblocks.vhdl, basicblocks.vhd, d_flipflop.vhdl, and d_flipflop.vhd. All of these files contain a valid entity and architecture of name "d_flipflop". I get the same result if the library directory is empty.

Error (10481): VHDL Use Clause error at tps2834.vhdl(34): design library "basicblocks" does not contain primary unit "d_flipflop"

Lines 34-41 of tps2834 are

u2: entity basicblocks.d_flipflop port map(

clock => not pwm,

preset => '1',

clear => enable,

d => continuous,

q => continuous_sample,

qbar => open

);

Does the definition of "primary unit" exclude entities and architectures? If so, what is an acceptable design unit?

I am aware of the nearly equivalent library design unit dff; I am pursuing this to clear up my understanding of how to create my own libraries.

@Rysc:

This works. It seems that the altera libraries are treated as standard vhdl libraries, but user libraries are not.

Cheers

John