I am working on the hardware implementation of RC4 cipher and has written the code for it using ASM design methodology and the key and plain text are given by the user through two input ports of integers. After running Analysis and Synthesis, the device uses around 800 pins and Altera Quartus II Web Edition supports FPGA having max pins of around 520. What should I do? I tried using pin assignment but didn't understand it. While I run the compilation, it shows that only a few pins, around 300 drive logic. How can I remove the useless pins? I need to do this because I have to compare RC4 basic version with its other versions like RC4+.
