inserting delay buffer at output pin of FPGA

[Altera_Forum]

hi all, 

 I want to add a small delay to one of my outputs, just to test/try out an idea. I need about 10-15ns, while my clock is 204ns period.  Looking around the web, I see some people using LCELL. Would this be the best thing to use, or another primative? The output I am trying to delay is not that of a register, but the output of a LUT. And I need this output to be delayed slightly with respect to another one of the LUT's output. Should I or can I somehow constrain the timing so this output A is 10ns delayed with respect to output B? (not with respect to a clock).

[Altera_Forum]

Perhaps one way to do it is to create a second clock with a pll that has the same period but is phase shifted by 10ns. Output A can be clocked on the initial clock's edge, while output B can be clocked on the phase shifted clock's edge. This way output A will update 10 ns prior to output B.

[Altera_Forum]

Using an additional tap from the PLL sounds like a reasonable option, and also will be compensated across voltage and temperature. If you go and insert logic in the path, you will get very different delays between slow and fast corner since the effect of process voltage and temperature in CMOS circuits varies greatly.