TTK .. having difficulties

[Altera_Forum]

http://www.alterawiki.com/wiki/use_transceiver_toolkit_to_measure_pci-express_link_signal_integrity 

 Using this reference design ... I tried with Quartus 13.1 and 14.0 and in both cases after loading the .sof and starting the TTK , the GUI comes up but I fail to get to step 5. It implies the TTK can't detect the reconfig_controller in the design ..  Since this is a reference design, I am not sure what is up ... Quartus 13.1 indicates altpcie_reconfig_driver.sv needs to be updated and 14.1 requires a re-generation of the RTL.  Any ideas ?  Thanks, Bob.  [h=3]Steps to run TTK[/h] 

1. Open the project in Quartus, must be 13.1 or later, installed in the computer which is connected to the FPGA through the USB blaster. 
2. Under pull down menu, select "Tools/System Console/Transceiver Toolkit", it opens the TTK window. 
3. Select "Transceiver Toolkit" tab. 
4. Select "Receiver Channels" tab, it allows you to measure and control the RX. 
5. Select the "reconfig" file in reconfig path pull down menu. If you don't see any file, it means the TTK can't detect the reconfig_controller in the design. Re-check the connection between the JTAG-to-AVMM Master and the reconfig_controller in Qsys. 
6. Add the channel number you want to measure or control into the field at the end of the Reconfig path. 
7. Click "Create Receiver Channel" icon to create the requested channel. 
8. Click "Control Receiver Channel", it opens "Receiver: Rx_channel_x" window. 
9. If the link speed is in Gen3 and the link is trained through standard PCIe link training, include EQ phase, the "Equalization Mode" should be in "one-time adaptation" as shown below. The value in "Equalization Control" field reflects the current RX CTLE setting. If the FPGA is Gen1 or Gen2 capable, since the AEQ is not enabled, so it does not show the "Equalization Mode" and the "Equalization Control" value is 0. 

[Altera_Forum]

Hi Bob, 

I used myself that example design as starting point for another altera dev kit that I had In attachment you can find my design: I used 13.1 without any problem.  I suggest you to check your Qsys connections as suggested in the wiki in particular that you connected the Jtag to avalon master port to the reconfiguration controller slave one.  If they are fine, verify that you're not keeping all in reset and that the clocks of your system are present at FPGA pins and at right frequency.  Anyway maybe a screenshot of what you've to do inside TTK could help. This is what happen to me in step 5 you're referring to: http://www.alteraforum.com/forum/attachment.php?attachmentid=10591&stc=1   Once you do that you can go under control receiver and start your tests to see that you've no error (or adjust equalization parameters if needed) http://www.alteraforum.com/forum/attachment.php?attachmentid=10592&stc=1  or also run the EyeQ to see the eye opening (in my case as you can see it is pretty open) http://www.alteraforum.com/forum/attachment.php?attachmentid=10593&stc=1   Last but not least you can check from QII the logical xcvrs name and physical pin used that you assigned previously in your compilation. http://www.alteraforum.com/forum/attachment.php?attachmentid=10594&stc=1   I attach you here my design, but as said it is not for the same board so I changed pinout and also some clocks if I remember correct (it was more than 1 year ago). I hope it helps  Cheers

[Altera_Forum]

Wow, some eye .... I wish I could get that ... the thing is the example I have is an Altera example ... and it should all be connected correctly if it is an example ... I get nothing on the TKK window ... the first one you have ... One thing is I have Quartus 13.1 on one PC and 14.0 on the other .. only the one with 14.0 gets the TTK to open ... possible I need if check if that is included in the Quartus download.... The note seemed to imply that with 13.1 s .sv file would need to be replaced and the design re-synthesized and .sof reloaded ... was that the case for you ... 

 On an unrelated subject ... I have “Gen3 x8 Avalon-ST 256-bit - Stratix V” design and it has excellent Inbound Gen3 x8 performance ... I want to add a BAR and On Chip Memory behind it to test Outbound preformance for Gen3 x8 ... I am not sure how to do that . Any ideas ... the HIP component says I can add BAR's but they don't appear as a Avalon MM master port on the component GUI is QSYS.  Thanks, Bob.

[Altera_Forum]

Hey Bob, 

 I'm in the process of writing a Transceiver Toolkit tutorial.  I was just at the point of using the TTK GUI under Quartus 15.0 and its broken, eg., you cannot control the transmitter at all (the start button remains greyed out), all sorts of other weird stuff. Using Tcl I can access the transceiver registers directly, turn on the loopback, pattern generator and checker, and confirm that the loopback link works fine. Some of these changes show up in the TTK GUI, while others do not.  I've just tried Quartus 14.1 and it has similar issues.  I'm about to go back to 13.0sp1 (since I have it installed), and will then try 13.1.  Let me know if you found a version of Quartus where things worked ...  Cheers, Dave

[Altera_Forum]

Hey Bob, 

 Ok, I've found a work-around.  With a single transceiver link, when TTK starts, the tx channel, rx channel, and link are present in the TTK GUI. Those default links do not work. If I delete the defaults and recreate them, things work. In an attempt to understand this, I looked on the Altera KnowledgeBase and found articles stating that TTK expects the PHY at address 0 and the reconfig controller at 0x800.  https://www.altera.com/support/support-resources/knowledge-base/solutions/rd07212014_396.html https://www.altera.com/support/support-resources/knowledge-base/solutions/rd07222014_165.html  I suspect that deleting the defaults and re-creating the channel resolves the issue with the "assumed" addresses of the defaults.  I'll change my addresses and see if the default channels work.  Cheers, Dave

[Altera_Forum]

Hi all, 

 I can confirm that creating the Qsys design with the PHY at address 0 and the reconfiguration controller at address 0x800 allows the Transceiver Toolkit default channel/link configuration to operate correctly.  Here's a couple of TTK images for an Arria V GZ board (Texas Instruments TSW14J56EVM).  https://www.alteraforum.com/forum/attachment.php?attachmentid=10625   https://www.alteraforum.com/forum/attachment.php?attachmentid=10626   Cheers, Dave