Need Up To Date Tutorial on Pin Assignments with Schematic Entry

[Altera_Forum]

I'm new to Altera Schematic entry tools for their FPGA's. I used Xilinx tools several years ago, but decided to give Altera a try. Anyhow, I downloaded the tutorial "tut_quartus_intro_schem.pdf" which does a fair, but out of date, job of explaining how to do a project. When I get to the pin assignment editor section, nothing works and nothing in the tutorial is compatible with Quartus II v15.0 that I just downloaded. There isn't a specific version given in the tutorial, but it was copyright 2008 which tells me that its out of date. 

 Is there a more current tutorial that is more appropriate to v15.0?  I searched and found a blurb that said "to assign the pin numbers, right click the pin and select 'assignment editor'", but of course, that isn't one of the options. I can go into the assignment editor directly, but there doesn't seem to be a logical way to assign the pins.   My goal here is to simply bring one of the pins on my netlist to a physical pin on the outside of the chip.  The old tutorial that I have been using had me draw out an XOR gate using AND-OR-INVERT gates. That compiles, but I'm stuck on the pin assignments.  Anybody know where a more up to date tutorial, or just one that explains the pin assignments better?  Thanks in advance.

[Altera_Forum]

While I do not use graphical input, I'd suggest to have a look into the QII help, which seems to be quite explainatory on "schematic pin assignment" :-)

[Altera_Forum]

--- Quote Start ---  While I do not use graphical input, I'd suggest to have a look into the QII help, which seems to be quite explainatory on "schematic pin assignment" :-)  --- Quote End ---    Been there, done that, no good. Help tells me to do things for some other version of software than v15.0. For example, right clicking and the context menu in the help is not what I see on the screen. I'm starting to think that the solution is to download an older version and forget about v15.0 for now.

[Altera_Forum]

More info:  

This is the tutorial that I have been using: ftp://ftp.altera.com/up/pub/digital_logic/de2-70/tutorials/tut_quartus_intro_schem.pdf  Its very good until I get to page 17 "Pin Assignments". At that point, v15.0 is too different for me to follow.

[Altera_Forum]

More easily, create your schematic entry, just run analisys and synthesis and then use the pin planner tool inside QII to give I/O assignment.

[Altera_Forum]

--- Quote Start ---  More easily, create your schematic entry, just run analisys and synthesis and then use the pin planner tool inside QII to give I/O assignment.  --- Quote End ---    Thanks. Here is what I did.  I clicked PROCESSING-> START-> START ANALYSIS AND SYNTHESIS  Then let it compile for a bit. When done, I clicked ASSIGNMENTS-> PIN PLANNER  My nodes were listed at the bottom of the screen so I just picked the pins I wanted from that. I could also pick the pin I wanted directly and change it to the node.   When that was done, I clicked PROCESSING-> START I/O ASSIGNMENT ANALYSIS It compiled again, but wasn't happy with my pin selections. I reassigned them, not sure if I did it right, but after a few iterations, the compiler reports 0 errors, 3 warnings. 1. Parallel compilation needs a license. 2. Logiclock needs a license. 3. Pins must meet Altera requirements for 3.3V interfaces and specifically names my two inputs.  I think I can probably ignore warning# 1. Not sure about# 2 because I don't know what logiclock is. Is# 3 just Altera's way of saying the pin is not 5V tolerant?  Anyhow, hopefully this will get me to the next step of the tutorial.

[Altera_Forum]

Hi, 

you need to compile your design once to have the Pin Planner provide you with a list of your design's signals. I'd forgot to mention this...  Regarding your warnings....# 1 and# 2 are informal, i.e. maybe your configurations includes a tick at "parallel compilation" and "logiclock", thus the WebEdition just tells you these features are available only in subscription version. # 3 is as you expected, seems like your target device is not 5V compatible, you'd check in the device's handbook either. The times of FPGAs with 5V I/O pins are generally long time gone. Even the support for 3.3V levels is significantly reduced meanwhile.