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Not sure where the correct place to post fixes are but found this minor issue. Obviously not a problem unless debugging he FPGA loading process.
49c49 < //# define dprintf(fmt, ...) printf(fmt, __VA_ARGS__) --- > //#define dprintf(fmt, ...) printf(fmt,# #__VA_ARGS__)Link Copied
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Thank-you for reporting, I filled a bug report on it. If you spot others can you feed them to Altera using "myAltera" link on this page: https://www.altera.com/support.html (that will speed up the fix)
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