I/O Timing constraints when clock is internally generated

[Altera_Forum]

Hi. 

 I have a state machine that drives output pins, and also has incoming signals from input pins. The state machine is clocked by the output of a PLL, and the same clock also drives a clock output pin. This is for connection to an external chip, (an ethernet PHY), that also has the I/O signals connected. Both sides are fully synchronous. (The PLL output is 50MHz).  I know the Clk-to-Out of the PHY, and its input setup requirements. I now need to apply Clk-to-Out constraints, and input setup constraints, for the Cyclone, with reference to the Clock output pin. (not the internal PLL output). How do I do this? I get 'nothing to report' in Timequest, for anything relating to that pin when I try to report the timing in 'Custom Reports'. The set_input_delay and set_output_delay constraints have been ignored, but no waring or error is generated during the flow.  I thought perhaps Timequest is not recognising that the state machine is related to the clock output pin, because it is defined as an output. So I changed it to an INOUT, and feed back into the chip and connect the state machine to that instead of the PLL output. Still nothing.  If I temporarily change the clock output pin to be INPUT, its OK, I can see input setup and Clk-to-Out information in timequest..... but of course I actually need my internal 50MHz to be the clock source.  I would have thought that this should be an easy thing to do - two fully synchronous interfaces connected to each other, a Cyclone and a PHY, and the PHY side is already defined. I need a clock pin to tx output delay of 2ns to 9ns, and a rx input setup to clock pin of 3nS to 9ns max.   ... I'm new to the Altera world, crossing over from Xilinx, so more familiar with UCF constraints....    Quartus II, 14.1 64-bit. Cyclone V 5CSEBA6U2317

[Altera_Forum]

If I understood, you clock from fpga to get data from phy chip. Hence your interface is not source synchronous as clock is opposite data direction. 

Use virtual clock to define data offset. In source synchronous inputs, the tool needs data offset from the clock (min and max). You need to work out this offset expressed relative to virtual clock but derived correctly.  You can either derive the offset relative to PLL input clock (if it is base clock) but you might get into trouble if its relation to the 50MHz is fractional.  You can derive offset relative to output clock as clock board delay from fpga to phy + phy tCO + data board delay from phy to fpga. enter computed min/max offset relative to virtual clock.

[Altera_Forum]

--- Quote Start ---  Hi.  I have a state machine that drives output pins, and also has incoming signals from input pins. The state machine is clocked by the output of a PLL, and the same clock also drives a clock output pin. This is for connection to an external chip, (an ethernet PHY), that also has the I/O signals connected. Both sides are fully synchronous. (The PLL output is 50MHz).  I know the Clk-to-Out of the PHY, and its input setup requirements. I now need to apply Clk-to-Out constraints, and input setup constraints, for the Cyclone, with reference to the Clock output pin. (not the internal PLL output). How do I do this? I get 'nothing to report' in Timequest, for anything relating to that pin when I try to report the timing in 'Custom Reports'. The set_input_delay and set_output_delay constraints have been ignored, but no waring or error is generated during the flow.  I thought perhaps Timequest is not recognising that the state machine is related to the clock output pin, because it is defined as an output. So I changed it to an INOUT, and feed back into the chip and connect the state machine to that instead of the PLL output. Still nothing.  If I temporarily change the clock output pin to be INPUT, its OK, I can see input setup and Clk-to-Out information in timequest..... but of course I actually need my internal 50MHz to be the clock source.  I would have thought that this should be an easy thing to do - two fully synchronous interfaces connected to each other, a Cyclone and a PHY, and the PHY side is already defined. I need a clock pin to tx output delay of 2ns to 9ns, and a rx input setup to clock pin of 3nS to 9ns max.   ... I'm new to the Altera world, crossing over from Xilinx, so more familiar with UCF constraints....    Quartus II, 14.1 64-bit. Cyclone V 5CSEBA6U2317  --- Quote End ---    It seems there is no constraint for PLL. Did you apply "derive_pll_clocks" constraint? Here's some example of the constraint https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_timequest_cookbook.pdf

[Altera_Forum]

Hi Kaz, Mini. 

 There are data paths in both directions.  For the tx path, the fpga drives clock and data to the PHY. The PHY setup time is 4ns and has a hold time of 2ns. Naturally, this is at the pins. I therefore want to constrain the fpga clock-to out, at the pins, to be minimum 2ns, maximum 16ns.  For the rx path, the FPGA is still clocking the PHY, and the PHY drives rx data to the FPGA with a clock-to out between 3ns and 9ns. I therefore want to constrain the fpga setup time to be no more than 11ns and hold time no more than 3ns. (Again at the pins).  Unfortunately, the PLL is fractional, as the input is 40MHz. (We can't change that, it's used everywhere else).   The 'derive_pll_clocks' entry has been there all the time. See below.   create_clock -period 20 [get_ports aux_eth_ref_clk] // output port, driven by 50MHz PLL output  derive_pll_clocks  set_output_delay -max 16 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_txd*] set_output_delay -max 16 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_tx_en] set_output_delay -min 2 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_txd*] set_output_delay -min 2 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_tx_en]  set_input_delay -max 11 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_rxd*] set_input_delay -max 11 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_rx_dv] set_input_delay -max 11 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_rx_er] set_input_delay -min -3 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_rxd*] set_input_delay -min -3 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_rx_dv] set_input_delay -min -3 -clock [get_clocks aux_eth_ref_clk] [get_ports aux_eth_rx_er]   What else do I need? The tools should know the skew between the clock that drives the state machine, and what appears on the clock pin, right??

[Altera_Forum]

Tx timing is typical source synchronous but your figures are wrong. You should set max to tSU of phy and min to minus tH of phy. 

 For Rx your interface is not source synchronous (destination synchronous) and data is opposite clk. You need virtual clock here. The data offset (max,min) = 3~9 tCO of phy + data board delay + clk board delay = say 4 ~ 10  I don't know if you can use output clk if you add generated clk statement.