i have question about verilog. i coudln't make one clock. will u help me please.

[Altera_Forum]

i attached file & picure. 

 our team creating uart verilog code. by using modelsim.  i have 4 modules for FPGA and one module for simulation as like testbench.  so i will explain shortly. in code, when transmit is 1, enable= 1 ( it create one clock)    transmit ________l------------l____________________ enable __________--___________________________  but, i coudln't fix that problem... when i run code, output wire enable is not connected.   the code is in '"module dld" Thank you.

[Altera_Forum]

we didn't put rx. we just put tx code. not rx.

[Altera_Forum]

You did not initialize the reset value for reg a and reg b in module "dld". Like reg a=0,b =0; Or change the always process like below 

always @ (posedge clk or posedge reset) if begin  a <= 0;  b <= 0; end else begin  if(counter == 12'd2604)   begin  a <= transmit;  b <= ~a;  end end

[Altera_Forum]

Thank you for your help. I appreciate. Haha thanks! I was not good yesterday about feeling but right now I feel happy ! Thanks again. Sleep well !! Good night

[Altera_Forum]

--- Quote Start ---  You did not initialize the reset value for reg a and reg b in module "dld". Like reg a=0,b =0; Or change the always process like below always @ (posedge clk or posedge reset) if begin  a <= 0;  b <= 0; end else begin  if(counter == 12'd2604)   begin  a <= transmit;  b <= ~a;  end end  --- Quote End ---    Thank you for your help. I appreciate. Haha thanks! I was not good yesterday about feeling but right now I feel happy ! Thanks again. Sleep well !! Good night