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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Accurate Powerplay Analyser results using Uniphy

Altera_Forum
Honored Contributor II
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I am trying to figure out some solution of getting accurate results (well at least ones that Quartus's metrics say are good) 

from the powerplay tool when using a uniphy block. 

 

From my understanding the normal method of getting power results with high confidence is to compile it, use the .vo  

file it spits out, run a gate level sim, create a .vcd file and then use the .vcd in powerplay. This would normally  

work but Altera specifically say you can't run gate level sim on Uniphy.  

 

I have gone through the following processes but each has their problems 

 

a) If I create a .vcd from my RTL simulation (modelsim) and then run it in powerplay, the confidence metric is low (30%) 

because a lot of the names don’t match up because powerplay is using the postfit netlist. 

 

b) If I simulate using a gate level file anyway from quartus e.g. .vo then generate the .vcd, the names match up but  

the design doesn't get out of memory calibration. I left it running for a week and it didn't get out of calibration. This  

means I am not getting a true representation of the signal activity since it is not running my design properly. 

The confidence level is high though as all the names match up.  

 

c) In the powerplay application note it mentions using incremental compilation to prevent net mismatches. I broke 

my design down in to separate partitions but the names are all still messed up compared to the RTL .vcd file. 

 

I can't believe that with all the memory cores altera has and how integrated PowerPlay is within Quartus that they  

don't have a solution for this. 

 

The crux of my question is  

 

How do I use powerplay analyser to create accurate power results when I am using a uniphy IP block in my design? 

 

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