ModelSim error

[Altera_Forum]

I can't run the simulator for my project because of these 2 errors. 

Did some research for fixes, but nothing is working yet. Any help is appreciated.   Determining the location of the ModelSim executable... Using: /home/lmj/apps/Quartus/modelsim_ase/linuxaloem/ To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off lab_2 -c lab_2 --vector_source="/media/lmj/E2B9-E082/YoungJackson_hardwarelab/lab_2/Waveform.vwf" --testbench_file="/media/lmj/E2B9-E082/YoungJackson_hardwarelab/lab_2/simulation/qsim/Waveform.vwf.vt" Inconsistency detected by ld.so: dl-close.c: 762: _dl_close: Assertion `map->l_init_called' failed! Info: *******************************************************************Info: Running Quartus II 64-Bit EDA Netlist Writer Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition Info: Copyright (C) 1991-2015 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus II License Agreement, Info: the Altera MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Altera and sold by Altera or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Sun Jun 14 06:05:32 2015Info: Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off lab_2 -c lab_2 --vector_source=/media/lmj/E2B9-E082/YoungJackson_hardwarelab/lab_2/Waveform.vwf --testbench_file=/media/lmj/E2B9-E082/YoungJackson_hardwarelab/lab_2/simulation/qsim/Waveform.vwf.vtInfo (201000): Generated Verilog Test Bench File /media/lmj/E2B9-E082/YoungJackson_hardwarelab/lab_2/simulation/qsim/Waveform.vwf.vt for simulationInfo: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1081 megabytes Info: Processing ended: Sun Jun 14 06:05:33 2015 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation --tool=modelsim_oem --format=verilog --output_directory="/media/lmj/E2B9-E082/YoungJackson_hardwarelab/lab_2/simulation/qsim/" lab_2 -c lab_2 Inconsistency detected by ld.so: dl-close.c: 762: _dl_close: Assertion `map->l_init_called' failed! Info: *******************************************************************Info: Running Quartus II 64-Bit EDA Netlist Writer Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition Info: Copyright (C) 1991-2015 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus II License Agreement, Info: the Altera MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Altera and sold by Altera or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Sun Jun 14 06:05:36 2015Info: Command: quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=/media/lmj/E2B9-E082/YoungJackson_hardwarelab/lab_2/simulation/qsim/ lab_2 -c lab_2Info (204019): Generated file lab_2.vo in folder "/media/lmj/E2B9-E082/YoungJackson_hardwarelab/lab_2/simulation/qsim//" for EDA simulation toolInfo: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1085 megabytes Info: Processing ended: Sun Jun 14 06:05:37 2015 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** /media/lmj/E2B9-E082/YoungJackson_hardwarelab/lab_2/simulation/qsim/lab_2.do generated. Completed successfully. **** Running the ModelSim simulation **** /home/lmj/apps/Quartus/modelsim_ase/linuxaloem//vsim -c -do lab_2.do Reading pref.tcl# 10.3d# do lab_2.do# ** Warning: (vlib-34) Library already exists at "work".# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct 7 2014# Start time: 06:05:40 on Jun 14,2015# vlog -work work lab_2.vo # -- Compiling module lab_2# # Top level modules:# lab_2# End time: 06:05:41 on Jun 14,2015, Elapsed time: 0:00:01# Errors: 0, Warnings: 0# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct 7 2014# Start time: 06:05:43 on Jun 14,2015# vlog -work work Waveform.vwf.vt # -- Compiling module lab_2_vlg_sample_tst# ** Error: Waveform.vwf.vt(31): near "-": syntax error, unexpected '-', expecting ')'# End time: 06:05:44 on Jun 14,2015, Elapsed time: 0:00:01# Errors: 1, Warnings: 0# ** Error: /home/lmj/apps/Quartus/modelsim_ase/linuxaloem/vlog failed.# Executing ONERROR command at macro ./lab_2.do line 4 Error.    OS: Ubuntu 14.04 LTS Quartus II version: 64-bit 15.0.0 Build 145 04/22/2015 SJ Web Edition No patches installed

[Altera_Forum]

Hi, 

 By looking at the message, it seems like there is syntax issue with the Waveform.vwf.vt file. If you look into the line 31 of the file, do you observe any anomaly? Probably some bracket not closed properly.

[Altera_Forum]

--- Quote Start ---  Hi,  By looking at the message, it seems like there is syntax issue with the Waveform.vwf.vt file. If you look into the line 31 of the file, do you observe any anomaly? Probably some bracket not closed properly.  --- Quote End ---    I went back and actually "looked" for the Waveform.vwf.vt using the find command in the terminal.   find / -type f -name "*.vt"  This gave me the location of all files ending with the .vt extension... found the one I needed and opened it up in the editor and went to line 31. Turns out that the compiler didn't like that I was using a dash in naming my inputs on the diagram. I renamed the inputs without the dashes and compiled again, everything works fine now.  thanks

[Altera_Forum]

Hi Lasec0203, 

 Glad to hear that you have managed to resolve the issue.

[Altera_Forum]

Generally I would use "_" instead of "-" to avoid syntax issue during compilation and simulation.