LE and memory blocks in a cyclone

[Altera_Forum]

Hello, 

 I'm quite new in the world of the FPGA, indeed, I'm an engineer student in end-of-studies internship which is about using a FPGA. Well, I'm telling you that because I guess that you will think my question is a question of newbies :oops:.  When I start studying FPGA, my teachers said that the most important characteristic of these devices is the number of Logic Elements. But during my internship, I did some architectures using IP and then, after a full compilation, I realized that the characteristic which constrained me the most is the "total memories bits". After few research, I understood this characteristic was the representation of the memories blocks (like M9K).   Here come my question, what is the constitution of a memory block? is-it a very important parameter in a fpga?   Example:  My FPGA have 600K memories bits and 22K LE. After Quartus compilation, I realize that my architecture need 500K memories bits but only 2K LE. can i use le instead of memories block for 1 or 2 ip?     I hope that I explained my problem clearly,  Thank in advance,  Clément.

[Altera_Forum]

I find memory bits not very useful, unless building really big RAMs and you might approach full efficiency. For example, if the FPGA has M20K blocks, which can be 20k1, 10kx2, etc. down to 512x40(look at data sheet for specifics), then if I build a FIFO that only needs a 256x8 size, the rest of the RAM is wasted. Because of this you usually run out of RAM blocks before actual bits.  

As for what's most important, it depends. Some run out of LEs, but some run out of memories, some out of DSP blocks, some out of general purpose I/O, some out of transceivers, some out of DDR3 interfaces, some out of PCIe interfaces, etc. By and large LEs are the most common, then probably memories and/or pins(transceivers nowadays).  You can build a memory out of logic, but it is really inefficient. For example, a 512x16 would not onlyr require 8K registers just to hold the bits, but you would have sixteen 512X1 muxes to read it, plus write address decodes to write each address. This adds a ton of support logic and runs really, really slow. Most of the time it's just not worth it, but it it possible in theory.

[Altera_Forum]

There is also the option of memory that isn't part of the FPGA chip itself. 

 Some FPGA dev boards also have simple to use parallel static RAM. These are easy to use, see the data sheet. If no you might have DDR memory. Much harder to use, but also much larger. If you need that, search for example projects for that particular board.

[Altera_Forum]

--- Quote Start ---  I find memory bits not very useful, unless building really big RAMs and you might approach full efficiency.[...] You can build a memory out of logic, but it is really inefficient. For example, a 512x16 would not onlyr require 8K registers just to hold the bits, but you would have sixteen 512X1 muxes to read it, plus write address decodes to write each address. This adds a ton of support logic and runs really, really slow. Most of the time it's just not worth it, but it it possible in theory.  --- Quote End ---    My problem is that with only 2 FIFO and 1 FFT on my cyclone IV, I'm approaching full efficiency of memory bits. But I use only 1/10 LEs of the FPGA.     --- Quote Start ---   Some FPGA dev boards also have simple to use parallel static RAM.  --- Quote End ---    But the goal of my internship is to implement a fully programmed FPGA (and only this device) on another system. So I can't use any peripherals available on the board.  However, I would like to know: If I use an external memory of FPGA chip, wouldn't FPGA be really slower than if I used only the internal memory?

[Altera_Forum]

--- Quote Start ---  My problem is that with only 2 FIFO and 1 FFT on my cyclone IV, I'm approaching full efficiency of memory bits. But I use only 1/10 LEs of the FPGA.   --- Quote End ---    Do you mean efficiency or utilisation? You use the memory efficiently when you use the memories without wasting any bits. If you created a 1k ram, but this ram is placed on an M9K, you have only used about 10% of the ram, and the other 90% is wasted, which is not very efficient. You can use up your ram very quickly like this.    --- Quote Start ---  However, I would like to know: If I use an external memory of FPGA chip, wouldn't FPGA be really slower than if I used only the internal memory?  --- Quote End ---    THere are trade offs: FPGA ram is has high bandwidth (because you access so much of it in parrallel) but has low capacity. External ram will be much lower bandwidth (as you only have one data bus, but the bandwidth will be determined by bus speed) but can have a huge capacity.  So it really comes down to your application. Example - if you are running video with a frame buffer, at larger resolutions a single frame would easy use most or all of the FPGA memory - so you need an external ram to store it.

[Altera_Forum]

--- Quote Start ---  Do you mean efficiency or utilisation?   --- Quote End ---    Well, actually I don't really know. To build my architecture, I just utilize 3 IP using the megawizard of Quartus and a top level to link them together. So, I guess Altera's IP use the memory efficiently.  And the problem is that in my poor little test, I use 500K of the 600K memory bit of my cyclone IV, so do you think I can optimize it?

[Altera_Forum]

Without having your design, we cannot say how to optimise it. 

But if you're using the megawizard, then it should be fairly efficient already. The high utilisation is because you set it up that way.

[Altera_Forum]

--- Quote Start ---  Without having your design, we cannot say how to optimise it.  --- Quote End ---   Well, actually my question wasn't right. I just want to know if it is possible to choose between LEs and memories blocks for an IP?  In fact, you didn't answer one of my first question which was : "what is the constitution of a memory block?".  Indeed, I easily find the constitution of a LE on the internet : http://www.ccciss.info/ciss420/ch2/cyclone.le.png  But I don't manage to find something who explain how a memory block is made.   At beginning, I was thinking that memory block was LEs already assemble to form an internal memory for the FPGA. Now, it seem like I was wrong.

[Altera_Forum]

--- Quote Start ---  Without having your design, we cannot say how to optimise it.  --- Quote End ---   Well, actually my question wasn't right. I just want to know if it is possible to choose between LEs and memories blocks for an IP?  In fact, you didn't answer one of my first question which was : "what is the constitution of a memory block?".  Indeed, I easily find the constitution of a LE on the internet : http://www.ccciss.info/ciss420/ch2/cyclone.le.png  But I don't manage to find something who explain how a memory block is made.   At beginning, I was thinking that memory block was LEs already assemble to form an internal memory for the FPGA. Now, it seem like I was wrong.

[Altera_Forum]

Well, to resume my interrogations and to up the thread, here a new question: 

 If I am constrain by the memories blocks but not with the LEs, can I choose to store my functions with the LEs and not with the memories blocks? And vice versa?

[Altera_Forum]

I think is default behavior to use LEs if you run out of memory block

[Altera_Forum]

LEs can be used as memory, but they are far less dense than ram. So you can quickly lose all your LEs to larger rams that have timing issues. LE rams are meant for small high speed applications.

[Altera_Forum]

But so, what do I do to store my functions with the LEs and not with the memories blocks? and vice versa?

[Altera_Forum]

See the "ramstyle" attribute 

 http://quartushelp.altera.com/14.0/mergedprojects/hdl/vhdl/vhdl_file_dir_ram.htm

[Altera_Forum]

--- Quote Start ---  See the "ramstyle" attribute  http://quartushelp.altera.com/14.0/mergedprojects/hdl/vhdl/vhdl_file_dir_ram.htm  --- Quote End ---    Thanks a lot !! That's exactly what I need.