FPGA PLL Megafunction

[Altera_Forum]

Hi Everyone ! 

 I am doing a project on an Altera Cyclone V FPGA. In this project I have a simple all-pass filter with severals I/O signals.  Now I need to implement a PLL so that the output clock of my filter becomes three times faster than the input clock.  So i created a Megafunction PLL with the wizard, and then I connected the output clock of my all-pass filter to the PLL input refclock.  Here are my questions :   - Is there a big difference between the ALTPLL (unavailable for Cyclone V) and the Altera PLL v13.0 (the one I use )? - From what I understood, the PLL is generated automatically from the wizard once you have set up the parameters you wanted for your PLL. I have a pll.vhd file which is generated, so I've done a structural file of my entire project which will be my top entity. Is it necessary to do it or is it done automatically thanks to the .bdf graphic file ?  - Then I can't simulate my project. I succeed to simulate my all-pass filter, but I can't simulate my PLL alone. And of course I can't simulate my entire project. The error returned tells me the design unit wasn't found ...  Hoping some of you can help Thanks in advance  David.

[Altera_Forum]

Hello David, 

 I think I would be able to help you in your third question.  When you use Altera PLL( Cyclone V ) in your design, you need to add following pre-compiled libraries in your simulation configuration : In case of verilog  (1) cycloneV_ver (2) altera_lnsim_ver  In case of VHDL,  (1) cycloneV (2) altera_lnsim  You can find precompiled libraries from following location : <Quartus Installation Path>\13.0sp1\modelsim_ase\altera  To add pre-compiled library, 

1. On the Simulate menu, click Simulate. 
2. If you are simulating a Verilog HDL design, to specify the ModelSim-Altera precompiled libraries: 
3. Click the Libraries tab. 
4. In the Search Libraries (-L) box, click Add and select the appropriate libraries. 
5. Click OK. 

 To get more idea about adding these libraries, Google should help you.  Let us know if you face any difficulty.  Cheers, Bhaumik

[Altera_Forum]

--- Quote Start ---  Hi Everyone !  - Is there a big difference between the ALTPLL (unavailable for Cyclone V) and the Altera PLL v13.0 (the one I use )?   --- Quote End ---    Hi,  Both are IPs used to instantiate and control the PLL in the Altera devices. The difference is that ALTPLL is used for devices older than V generation ie Cyclone IV while the Altera PLL is for V generation and above ie Cyclone V.

[Altera_Forum]

"- From what I understood, the PLL is generated automatically from the wizard once you have set up the parameters you wanted for your PLL. I have a pll.vhd file which is generated, so I've done a structural file of my entire project which will be my top entity. Is it necessary to do it or is it done automatically thanks to the .bdf graphic file ?"  

 Hi David,  Specific to your question# 2, is it that you are referring if you would need to add the pll.vhd file to your project? As I understand it, by default, after you create a project and instantiate a PLL, Quartus II will ask if you would like to add it to your project. Once it is added, you should be able to link to the PLL from your top level. alternatively, you can also manually add the file by Settings -> Files, then browse to your design files and add them into the project.

[Altera_Forum]

Thank you for your answer, I really Appreciate the Help,  

 Thanks for the tip "bfkstimchan", Tanks to you now I know i'm not using the wrong PLL  Yes "nic_@ ", I've done it and added the PLL.vhd file which was generated and then I succeffully added the PLL to the top level by writing a structural code of my project. Thank you, it confirms what I thought about the creation of the PLL Megafunction.  I followed what you said "Bhaumik" I added the libraries you talked about, but I still have an error occuring during the RTL compilation, telling me that this is a nativelink error and that it failed to make the ip-make-simscript. I can simulate my all-pass filter witout problems but not my PLL alone and not my complete design.  I don't know if you can help me on this one, i don't know where the problem is from. Anyway I think the PLL work, once I implement the binary file in the FPGA I see some differences. But It would be better to be able to simulate it before implementing it in the device...  Thank you all !  David.

[Altera_Forum]

David,  

 I think the easiest way to simulate your PLL is to use the NativeLink. I think i understand the difficulty of including the libraries and have simluation running. So far, Nativelink is working fine and simulating with Modelsim. Run nativelink --> Select the your PLL --> Create waveform --> on the waveform tab, edit waveform --> Export waveform  It will help create a testbench. edit the testbench if needed. Add your testbench in Quartus settings. Close Modelsim, and invoke it again.  You would see your simulation results.

[Altera_Forum]

Thank you for the advice "nicejob",  

 I will try what you said, I think it will be easier rather than including the libraries, With the Oscilloscope I can see that my PLL is working, but It's better to be able to visualize the simulation !  David