Error appending bits to std_logic_vector

[Altera_Forum]

I'm trying to do a very simple multiply by shifting and some adds. Here are the arrays i am using.  

 type pixel_array is array(8 downto 0) of std_logic_vector(7 downto 0); signal gaussianPixels : pixel_array; -- 3x3 array of pixels to be used for gaussian blur  type gaussian_partial_sum_array is array(2 downto 0) of std_logic_vector(15 downto 0); signal gaussianPartialSum : gaussian_partial_sum_array;   I'm trying to multiply (3) by 2 and add it to (0) and (6). since they're all multiples of 2 im trying to just implement this with shifts as follows.   gaussianPartialSum(0) <= ((7 downto 0 => '0') & gaussianPixel(0)) + ((3 downto 0 => '0') & gaussianPixel(3)& (3 downto 0 => '0')) + ((7 downto 0 => '0') & gaussianPixel(6));  But when I compile this, quartus give me an error saying:   Error (10327): VHDL error at top.vhd(377): can't determine definition of operator ""+"" -- found 0 possible definitions  Am i doing something wrong? i found some code online that showed that this is the way to do this.   many thanks for your help!

[Altera_Forum]

You can't add (to) vectors. You have to cast to unsigned or integer and then back.

[Altera_Forum]

You cannot do arithmatic on the std_ logic vector type. You need to include the numeric std library and use the unsigned and signed types. You should probably declare your arrays using then to.

[Altera_Forum]

--- Quote Start ---  You cannot do arithmatic on the std_ logic vector type. You need to include the numeric std library and use the unsigned and signed types. You should probably declare your arrays using then to.  --- Quote End ---    Thanks! that did the trick.