How to use the "Debounce Operation" for a Cyclone V.

[Altera_Forum]

I would like to use the "Debounce Operation" for a Cyclone V GX, 5CGXFC5C6F27C7N, on a Terasic "Cyclone V GX Starter Kit." The starter kit uses a Schmitt-Trigger buffer on the board to reduce bounce from the momentary switches. Unfortunately, it is its not good enough and I'm still getting a debouncing problem.  

 The Cyclone V Device Handbook, page 3137, section functional description of the gpio interface, subsection debounce operation, states, "The GPIO modules provided in the HPS include optional debounce capabilities. The external signal can be debounced to remove any spurious glitches that are less than one period of the external debouncing clock, gpio_db_clk."That is the feature I would like to use.   Question 1. Does the version of the Cyclone V GX I am using support that Debounce Operation? As the Debounce Operation is described in the HPS section of the manual, I am concerned that my Cyclone V GX does support HPS.       Question 2. Using Quartus II, V15.0.0, I am using schematic entry, i.e., Block Editor, to create a program to be downloaded to the "Cyclone V GX Starter Kit." The program is working fine except for the bouncing issues. How do I implement the Debounce Operation? I looked in Pin Planner and IP Catalog but saw nothing relevant. I did Google and Altera Forum searches on gpio_db_clk with nothing helpful.     I do know how to implement a debouncing circuit using flip-flops but if the capabilities is already built into Quartus II, I'd prefer to use that feature.     Thank you. :cool:

[Altera_Forum]

Since the GPIO interface you are talking about is on the HPS, there aren't any settings in Quartus for this. You will need to set it in software. Debounce is set in the gpio_debounce register. Once you've built the preloader, check the generated documentation files for the software library. There should at least be some register definitions for the gpio_debounce register you can use for this. There may (or may not) be a higher level routine to set debounce.

[Altera_Forum]

Galfonz, 

Thank you for the quick reply. I'll need some more details to be able to implement as almost everything I have ever done with an Altera FPGA has been done via Quartus II. What "software" are you referring to when you say, " You will need to set it in software?" Can you give me some key words so I can do some research on what this "software" is and how to use it?  Much thanks, Al

[Altera_Forum]

Looking back over your question, I realize my answer above doesn't apply to you. The "Functional Description of the GPIO Interface" section of the Cyclone V handbook you refer to describes the GPIO interface of the HPS side of the SoC chip. You aren't using an SoC so that doesn't apply. There is no built in debounce on the normal FPGA pins.  

This link https://www.eewiki.net/display/logic/debounce+logic+circuit+(with+verilog+example) might work for you but its fairly large. There are numerous other examples of how to do debounce on the net as well.