Hi,
I'm currently developing a project using the schematic design in Quartus 13.0. There, I have included 4 memory blocks using the RAM (megafunction). It seems that I have a problem with 2 of them when I'm trying to run its timing simulation (the functional simulation works fine). This is one of the several errors (all of them are very similar, referring to the same blocks, but referring to different inputs, such as addr_b_register, addr_a_register...):
# ** Error: c:/altera/13.0sp1/modelsim_ase/win32aloem/../altera/verilog/src/cycloneii_atoms.v(480): $hold( posedge clk &&& reset:1953042 ps, d:1953270 ps, 234 ps );# Time: 1953270 ps Iteration: 0 Instance: /Processador_vlg_vec_tst/i1/\inst12|inst|inst36|altsyncram_component|auto_generated|ram_block1a2 /addr_b_register Do you have any ideas on how to get this fixed?
Thank you!
