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Hi ,
Is there any report showing how many pipeline stages / stall clocks (using NDRrange - Multi-threads) by using aoc command ? Thanks.Link Copied
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The reports that altera provides are very limited. The optimization report in <kernel>/<kernel>.log contains some optimization reports but not a lot that occasionally shows inferred pipeline stages when you build the .aocx. You can check stalls/occupancy and bandwidth of memory access by running the profiler when you compile the kernel with --profile.
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You can open the project file top.qpf under the file folder bin_nameofkernel and you can find how many pipeline stages in the Tools/Netlist Viewers/RTL viewer
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--- Quote Start --- You can open the project file top.qpf under the file folder bin_nameofkernel and you can find how many pipeline stages in the Tools/Netlist Viewers/RTL viewer --- Quote End --- I was looking for a way to get that information ! Although I followed your instructions, I wasn't able to find the number of cycles in my pipeline. Instead I get a couple of numbers regarding the ALMs used by my design (see below). http://www.alteraforum.com/forum/attachment.php?attachmentid=11105&stc=1 Anyway somebody can help figure out how to get the information i'm looking for? A screencap would be more than welcome too ! Cheers !
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I think this only works for single task work items. The optimizations report are in the log if your kernel is a single task.
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Hi there,
I'm trying as well to understand how to get this information. Using the instructions above I opened Quartus II and then using file->open project to select the wished top.qpf file. At this point I had a screen like the one posted by vsenicourt. After that, using the menu Tools, netlist viewers->rtl viewers showed me a new window like the one in the image attached but I could get the number of stages in the pipeline. The project I'm using is the Fast Fourier Transform OpenCL Design Example from Altera which launches a single work item hence enqueues a task.- Mark as New
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Searching in the forum I found out this old post (http://www.alteraforum.com/forum/showthread.php?t=41198) where it's said that:
--- Quote Start --- The use model of the OpenCL compiler is that you don't need to worry about the pipeline depth because it will already be tuned to ensure that enough work-items are in flight to keep the pipeline full. --- Quote End --- But still, I think it would be nice to have some info about the pipeline.- Mark as New
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As somebody who is interested in parallel architectures and optimization, I strongly agree.
I want to know how much parallelism I can extract from playing on the depth of my pipeline (through loop unrolling, or change in instructions...), and put this number in front of potentiel other designs (that will essentially differ in width or number of pipelines), or even other parallel architectures.- Mark as New
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Exactly, also some information about bubbles and the initiation interval would be nice.
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