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SignalTap issue

Altera_Forum
Honored Contributor II
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I update my QII to 14.1, and met a SignalTap issue like the image shows: 

http://www.alteraforum.com/forum/attachment.php?attachmentid=10901&stc=1  

 

 

Why only partial samples have the wave, most spaces are blank? 

 

The Siganltap's setting is same as i did in QII12.1: 

http://www.alteraforum.com/forum/attachment.php?attachmentid=10902&stc=1
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Altera_Forum
Honored Contributor II
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I'm having the same problem. In addition to the missing sample data, signaltap ignores any trigger condition and just auto triggers. If I remove some signals and recompile it sometimes will work normally. I haven't figured out yet why including certain signals causes this problem.

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Altera_Forum
Honored Contributor II
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In the release notes for quartus 15 ( https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/rn/rn_qts_dev_support_update.pdf ) it mentions this problem: "Fixes an issue that causes the Storage Qualifier feature of the SignalTap™ II Logic Analyzer to miss samples." I'm not sure if there is a work around for 14.1 but, as with many issues, it looks like the fix is to upgrade to quartus.

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

In the release notes for quartus 15 ( https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/rn/rn_qts_dev_support_update.pdf ) it mentions this problem: "Fixes an issue that causes the Storage Qualifier feature of the SignalTap™ II Logic Analyzer to miss samples." I'm not sure if there is a work around for 14.1 but, as with many issues, it looks like the fix is to upgrade to quartus. 

--- Quote End ---  

 

 

Hi niccur, 

 

Thanks for you information. 

 

It's very strange, the same project can work well in QII12.1. 

 

BTW, I update from 12.1 to 14.1 and encounter this issue. Then i update to 15.0, the issue still happens.
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Altera_Forum
Honored Contributor II
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I'm having the same problem with SignalTap ignoring my trigger using QII 14.1. Before finding this post I got to the point of bringing my trigger signal out on a pin and triggering a logic analyzer off of it (which obviously worked just fine). 

 

Before I go installing different versions of QII to see which one works I wanted to see if anyone had identified which versions of QII come with a working SignalTap II version.  

 

The really odd thing is when I manually start and stop an analysis in SignalTap using version 14.1 the transitions are clearly visible in the captured data, SignalTap just does not trigger on them.
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Altera_Forum
Honored Contributor II
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It works well in QII13.0sp1.

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Altera_Forum
Honored Contributor II
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Thanks, I tried QII 13.1 but for some reason I'm getting compile errors, will have to correct that. 

 

I also tried QII 14.0 and SignalTap did not function correctly.
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Altera_Forum
Honored Contributor II
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Hi guys, 

has any of you figured out yet how to fix this random bug on ST ? 

I'm currently using Quartus Prime Pro 16.0 with an Arria 10 chip and I firstly thought that this bugs where related to the fact i'm using an Engineering Sample thus JTAG might have been buggy. But reading what was posted on the forum i see that I'm not alone and it might no come from what i expected. I noticed that i sometimes compiled 3 times the same design with no changes between compilations and i would get this bug to occur on 1/2 or 3 of my signaltap instances independently and randomly. I'm really lossing time on recompiling my whole design just to get SignalTap to work once. Here are the different issues i get (note that i don't get any timing issues): -"waiting for clock" (the compile after that he'll find it ...) 

-"Offloading data" when there is no trigger or triggering directly after i start  

a capture on something mysterious. 

- Oflloading some piece of data and not the full depth 

I really feel like this problem might be related to Place and route or JTAG issues with my hardware. 

If you found out , let me know.
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Altera_Forum
Honored Contributor II
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Hi everybody, 

even if this thread is quite inactive, here is what i found out about this problems. Apparently you need to make sure that all inputs and outputs related to the JTAG interface are constrained, especially the clock. This has been the answer given by Altera when opening a service request. After constraining this aspect of my design i didn't experience other bugs like this. So it's worth checking. 

I hope my answer will help others, this problem being very rare apparently and i didn't see any other answers concerning this problem.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Hi everybody, 

even if this thread is quite inactive, here is what i found out about this problems. Apparently you need to make sure that all inputs and outputs related to the JTAG interface are constrained, especially the clock. This has been the answer given by Altera when opening a service request. After constraining this aspect of my design i didn't experience other bugs like this. So it's worth checking. 

I hope my answer will help others, this problem being very rare apparently and i didn't see any other answers concerning this problem. 

--- Quote End ---  

 

 

YannnickLP, 

 

I to am using an Arria 10 with Quartus Prime Pro 16.0.1.... I have several problems but two of them are: 

 

1) I can't seem to move the trigger point to anything other than "Post Trigger Position"  

2) It doesn't seem to be actually triggering on what I'm setting up but rather just free running frame after frame. 

 

When you say "constrain the jtag signals" I'm not quite sure how you mean that. I see a section called JTAG signals in the "Quartus Prime Timequest Timing Anaylizer Cookbook"... Is this what you're talking about? 

 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_timequest_cookbook.pdf 

 

thanks, 

david
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Altera_Forum
Honored Contributor II
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hi David, 

in my case i had to add this constrain in my top sdc file : 

# ************************************************************** 

# Create Clock 

# ************************************************************** 

create_clock -name {altera_reserved_tck} -period 30.303 [get_ports {altera_reserved_tck}] 

 

the values might be different in your case even though i think these are the ones to be used. 

the "altera_reserved_tck" is the one clock used to drive JTAG so constraining it can not harm your design. 

In my case this seemed to stop the weird results i was having on SignalTap. 

Tell me if you need more information. 

 

Yannick
marcustx
Beginner
2,607 Views

I have had that issue and fixed it.

 

In my case, I had a "set_false_path" to the signaltap instance, by removing it, it solved the missing sampling and was able to also set triggers.

Hope this can help anyone else.

 

Marc

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