Pessimistic Timing Analysis

Altera_Forum · ‎07-21-2015

Hi

I have a design running on Cyclone III. My design is constrained and it works on physical hardware; but there are some errors in the output data processed and generated by FPGA. SO we have a working design which works on say 80 % of boards and is erroneous on 20 % of boards.

Of course that you may say everything could cause this problem, but since this situation occurs when I generate an additional output I think it is not an issue with board.

Timing failure is the most suspicious issue, but on other boards I have no problem with the same input data. This means that my timings are marginal and on some FPGAs this timing is met and on some others not.

How can I do a pessimistic timing analysis, so that I would be sure that timing failure will never occur on any FPGA part despite process variations on different dies?

Thanks

Altera_Forum · ‎07-21-2015

Hello msj,

You should have a correctly constrained design and you have to check all timing models from TimeQuest (ex. Slow 85C, Slow 0C, Fast 85C, Fast 0C, etc..) to see if they meet your requirements.

Where have you bought chip?