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Not able to complie NCO entity

Altera_Forum
Honored Contributor II
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Hi there,  

I have used NCO in my project. When i compile i get an error as  

 

Error (12006): Node instance "inst18" instantiates undefined entity "NCO13" 

 

 

Can anyone help me to resolve this error?  

 

Thank you in advance
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Altera_Forum
Honored Contributor II
872 Views

hi, 

is it possible to see the part of your hdl code containing the instantiation? 

thx
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Altera_Forum
Honored Contributor II
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I have attached the bdf file. Please look into it.  

 

Thanks, 

amod
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Altera_Forum
Honored Contributor II
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this is the vhdl code.

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Altera_Forum
Honored Contributor II
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I think i am missing a library.

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Altera_Forum
Honored Contributor II
872 Views

There are inconsistencies in the info you've posted with references to 'NCO13' in the error but references to 'NCOex' and 'NCO2' in the block diagram and VHDL respectively. Please make sure you are consistent. 

 

However, fundamentally Quartus doesn't know where to find the design entity - what 'NCO' is. How did you create NCO - via the IP Catalogue (or MegaWizard)? Are the source files for the IP included in your project? As indicated when you generate the IP 'you must manually add the .qip and .sip files after generating the ip core.' Or you can add the IP's .qsys file. So, check under 'Project' -> 'Add/Remove Files in Project...' that there are some files included for your IP. If not, add them. 

 

Cheers, 

Alex
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Altera_Forum
Honored Contributor II
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i d on't figure why you called it "NCO13". It must be called "NCO2" as you named it. Pretty sure that's why you get an error.

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Altera_Forum
Honored Contributor II
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Hi alex,  

 

I am sorry about the confusion. I tried multiple projects. I have created using Mega wizard option. I remember when created the NCO symbol, in my generation report it was not finished. I had to cancel the process. Manually add the symbol. Do you think this might be the case for not compiling?  

 

Thanks, 

Ash
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Altera_Forum
Honored Contributor II
872 Views

Screen shot of the generation report

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Altera_Forum
Honored Contributor II
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hi,  

if i use your vhdl file i would write this in the top level entity: 

nco_inst : nco13 port map( 

clk => clk_in, 

reset_n => reset_n 

... 

); 

 

and one more thing i noticed in the first vhdl file you sent : 

look at reset_n and clk_en, they got the same signal "clk_en".  

I doubt that reset_n has the same polarity than clk_en.
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Altera_Forum
Honored Contributor II
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Is 'nco13.qip' included in your project? Check under 'Project' -> 'Add/Remove Files in Project...' 

 

Cheers, 

Alex
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Altera_Forum
Honored Contributor II
872 Views

Thank everyone for helping out.

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