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Hi. I trying to attach Aleta SOST LVDS to my project, but I have next error:
Error (15065): Clock input port inclk[0] of PLL "lvds_tx:u17|lvds_0002:lvds_inst|lvds_tx_pll" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control blockWhen I trying to fix it, I find next warning: Warning (10036): Verilog HDL or VHDL warning at lvds_0002.v(561): object "dffe19a" assigned a value but never read I think this is a reason of my problem. Please help me to fix it. Thank you- Tags:
- lvds
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It seems like the refclk input of your soft LVDS is not connected properly. What is connected to the refclk pin of the soft LVDS? is it directly to an input pin in Quartus II design?
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Try connect the inclk of the LVDS instance to an input pin and run compilation to see.
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Hi,
Just to check if the issue resolved?
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