Use different voltages on GPIO

[Altera_Forum]

Hi, 

 Small summary: I am using GPIO ports on a Stratix-IV based board to interface it with a PCB that has an optical switch. I am using the GPIO ports to dynamically control the switches, by applying a given voltage to tune them. The problem is, even for passive behaviour of the switches, they need a small voltage to be applied. On the FPGA side, I can set the output to be either 1 or 0, being 1 my configured voltage (2.5V).   So, here is my question, can I specify the voltages on GPIO ports for both logical states? Let`s say, define a logical 0 to be 0.7 V and a logical 1 to be 3.3V?   Thanks in advance!

[Altera_Forum]

You can choose I/O Standard (ex. LVTTL, LVCMOS) but actual voltage depends also on voltage VCCIO on your board

[Altera_Forum]

Thanks for your reply! 

 If you please, could you give me a bit more explanation on that? I know how to set the default voltage for the pins, on the Pins Planner, but how would I set two different voltages, one for logical 0 and one for logical 1?  I am using a High global tech board, Stratix IV, device EP4S100G2F40I2.

[Altera_Forum]

You can't set any voltages, you need to pick I/O standard as flz47655 writes. Look which standard is closest to your needed voltage level.

[Altera_Forum]

You can't change it from Quartus, the VCCIO is the actual voltage applied by the board to the FPGA's VCCIO pins. Once it has been defined on the board level it can't be changed. 

You can find an explanation of the I/O features here (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/stratix-iv/stx4_siv51006.pdf) and the datasheet with the voltage levels here (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/stratix-iv/stx4_siv54001.pdf). I don't know how your board is wired, but if there is a correct voltage on the Vref and Vtt pins, you may be able to use a SSTL standard. Another alternative could be to use LVDS, but as it is a differential standard output pins are always used as pairs, with one pin having the opposite voltage level than the other. Both solutions are hacks really, but it all depends on how the FPGA pins are connected on your board.

[Altera_Forum]

--- Quote Start ---  Thanks for your reply!  If you please, could you give me a bit more explanation on that? I know how to set the default voltage for the pins, on the Pins Planner, but how would I set two different voltages, one for logical 0 and one for logical 1?  I am using a High global tech board, Stratix IV, device EP4S100G2F40I2.  --- Quote End ---    You should check on the IO specs requirement between the two devices that you want to interface with. For example, check on the interface partner of the SIV device. Determine the IO standards or IO specs. Then cross check with the device datasheet and select one that is compatible or meet the partner's specs.

[Altera_Forum]

Note that you could set different IO standard to each specific SIV IO pins but you would need to double check on the IO power supplies requirement ie VCCIO, VCCPD if you want to place these pins into the same bank.

[Altera_Forum]

--- Quote Start ---  Let`s say, define a logical 0 to be 0.7 V and a logical 1 to be 3.3V?    --- Quote End ---   You can't do this, you can select from preset logical levels throught I/O standards but voltage on the board (VCCIO) should be compatible

[Altera_Forum]

You can look into the SIV device datasheet, "I/O Standard Specifications" section to find out the VIL and VIH threshold voltages to determine the logical levels.

[Altera_Forum]

like flz47655 said, you may choose the IO standard which has the closest VIL and VIH threshold voltages by referring to the datasheet specs. You might also need to run signal integrity simulation to double check on the voltage swing as it will have dependency on your board setup.