Intel® Quartus® Prime Software
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not able to see the output on the oscilloscope

Altera_Forum
Honored Contributor II
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Hello everyone, 

 

I have programmed my FPGA De0 nano board to generate short pulse of 1000 ps and the time between the next pulse is 10 us. I want to see this pulse on digital oscilloscope. I have made all the connection from the DE0 board to the scope. is it possible to see the pulse on the scope. If possible, how can i achieve it?  

 

Thanks, 

amod
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Altera_Forum
Honored Contributor II
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Hi amod, 

 

I think the first thing to check is to run a Modelsim simulation to ensure your design function as expected. Then cross check on the pin out. You may send some clock pattern to see if scope capture it. Then only use your pattern.
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Altera_Forum
Honored Contributor II
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Hi nic, 

I have done that. able to see the simulation output. But not able to see the short pulse on the scope.
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Altera_Forum
Honored Contributor II
508 Views

Your scope have enough bandwidth and triggers are set right?

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Altera_Forum
Honored Contributor II
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Can you share your design? Even LVDS transmitter on the best speed grade device makes only 420 MHz. The other interfaces are way slower than LVDS. How you are trying to achieve one Gigahertz?

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Altera_Forum
Honored Contributor II
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You're not going to be able to generate the 1GHz clock needed for a 1ns pulse on a DE0-Nano. The max output frequency of the PLL is 472.5MHz. Your oscilloscope's not going to see something that isn't there. 

 

Cheers, 

Alex
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Altera_Forum
Honored Contributor II
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Yeah, there is no way to generate 1 GHz pulse on DE0-Nano

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Altera_Forum
Honored Contributor II
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DE0-Nano is with CIV E device. As Alex said, the max PLL output frequency for CIV E device is 472.5MHz only. Even if you are using LVDS, the max data rate is 840Mbps only.

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