Is this a bug?

Altera_Forum · ‎09-03-2015

While using the left-to-right stream operator in Modelsim Altera Strater Edition 10.1e with the following code:


module stream_bug();
bit  stream='{32{1'b0}};
initial begin
    $monitor("@%0dns stream= %b",$time, stream);
   # 1 stream={>>{8'b11010001}};
   # 1 stream={>>{ 'b11010001}};
end
endmodule

The output is:# @0ns stream= 00000000000000000000000000000000# @1ns stream= 11010001000000000000000000000000# @2ns stream= 00000000000000000000000011010001

Shouldn't the "stream" value be the same in 1ns and 2ns?:confused:

Altera_Forum · ‎09-03-2015

No "8'b11010001" is a 8 bit sized number but " 'b11010001" is a simulator defined sized number, but at least 32 bit.

It is a common misconception that a ticked(') number without an explicit size is automatically sized based on the usage in that particular usage but that is not true. It is essentially the simulator default size.

So you either packing in 8 bits or however many bits the simulator feels like giving you.

Altera_Forum · ‎09-04-2015

--- Quote Start ---

No "8'b11010001" is a 8 bit sized number but " 'b11010001" is a simulator defined sized number, but at least 32 bit.

It is a common misconception that a ticked(') number without an explicit size is automatically sized based on the usage in that particular usage but that is not true. It is essentially the simulator default size.

So you either packing in 8 bits or however many bits the simulator feels like giving you.

--- Quote End ---

I think that's the case. Thanks:D

Altera_Forum · ‎09-04-2015

There are no longer any simulator dependent sizes in Verilog or SystemVerilog. All numeric literals have an explicit or implicit size.

A numeric literal without an explicit size will be the larger of either: 32 bits or the number of bits needed to express the literal.

See http://www.eda.org/svdb/view.php?id=1107