Cannot write using FPGA2HPS and FPGA2SDRAM AXI ports

[Altera_Forum]

Hi everyone! 

 I'm currently in the process of transferring some IP cores with AXI interfaces from the Zynq to the Cyclone V SoC. However, while reading from the DDR memory using an AXI master port worked like a charm, I have major problems with writing to it.  In particular, I can't write to the memory at all as the AWREADY signal never becomes high, regardless of whether AWVALID is low or high and apparently also regardless of AWADDR. I observe the same behavior for both the FPGA2HPS and the FPGA2SDRAM ports. As mentioned before, in both cases reading data from the memory works just fine.   a) Does this ring a bell for anyone? Could it be a bridge configuration problem or a memory security issue? I looked for both but couldn't find any explanation for this behavior.  b) Does anyone know of any examples or reference designs in which a core in the FPGA acts as an AXI master? I could only find such designs for AXI slaves...   Best, Matt

[Altera_Forum]

Just in case someone has the same problem: I found out that in fact the AWREADY signal from the FPGA2SDRAM port to the AXI interconnect was working just fine. However, the AWREADY signal from the AXI interconnect to my IP core was stuck at 0.  

 In the end I "solved" my problem by re-importing my IP core into QSYS and marking my AXI master port as an AXI3 port. Originally, I had marked it as an AXI4 port although I only used the AXI3 functionality. Apparently, something went wrong with the translation from AXI3 to AXI4.