Does Quartus II 12.1 support Systemverilog 2005 in the following form?

[Altera_Forum]

Hi all, 

 It reported errors when using quartus ii 12.1 synthesis code with setting VERILOG_INPUT_VERSION SYSTEMVERILOG_2005. I paste it as bellow. http://www.alteraforum.com/forum/attachment.php?attachmentid=11928&stc=1  It can run pass if change it like this : http://www.alteraforum.com/forum/attachment.php?attachmentid=11929&stc=1  I looked up IEEE-std-verilog2005 ,and found that both with the keywords generate and without are ok. I also looked up quartusii_handbook13.1 and websit :http://quartushelp.altera.com/current/#hdl/vlog/vlog_list_sys_vlog.htm ,but cannot find whether quartus 12.1 support it or not.  Could you tell me the reason and how to solve this problem if it must be used without keyword generate? Thanks!

[Altera_Forum]

If it doesnt work - then I guess it doesnt work - I think you answered your own question.

[Altera_Forum]

PS. Quartus (and Vivado) has always picked specific parts of VHDL, Verilog and System verilog that they support. They never claim have full language support.

[Altera_Forum]

Are your missing the genvar declaration?

[Altera_Forum]

--- Quote Start ---  PS. Quartus (and Vivado) has always picked specific parts of VHDL, Verilog and System verilog that they support. They never claim have full language support.  --- Quote End ---     Yes, you are quite right. I also found what it described in handbook is like this: http://www.alteraforum.com/forum/attachment.php?attachmentid=11942&stc=1  I just can't find the accurate description of the way to use generate construct.  Thank you very much!

[Altera_Forum]

Yes , it was declared at the beginning of the module.