Exporting PLL outputs through conduits in Qsys

[Altera_Forum]

Hi all, 

   I am working on a FPGA design using Qsys software, however, I have some problems connecting signals among components.  In the figure that I have uploaded you can see a part of the global system. Basically, it is an Altera PLL core (from Qsys library) that synthesizes two clock signals from an external oscillator, and a customized subsystem that deals with an analog-to-digital converter and a digital-to-analog converter. The signals generated by the PLL are used both to drive the internal logic of each subsystem, and to provide clock signals to the external converters. The customized subsystem has two clock inputs, and two conduit inputs (red lines). the problem is that i can't connect outputs of pll to normal inputs of the other subsystem. anybody know how could i do it?  http://www.alteraforum.com/forum/attachment.php?attachmentid=11954&stc=1  

[Altera_Forum]

You said: "The customized subsystem has two clock inputs, and two conduit inputs (red lines). " shouldn't this be " ...and two conduit outputs (red lines). ". These outputs connect to pins in your FPGA which you connect to your external subsystem inputs. Why can't they drive your external subsystem? Do you have a square wave (clock signal) on these pins before you connect them to the inputs of your external subsystem?

[Altera_Forum]

--- Quote Start ---  You said: "The customized subsystem has two clock inputs, and two conduit inputs (red lines). " shouldn't this be " ...and two conduit outputs (red lines). ". These outputs connect to pins in your FPGA which you connect to your external subsystem inputs. Why can't they drive your external subsystem? Do you have a square wave (clock signal) on these pins before you connect them to the inputs of your external subsystem?  --- Quote End ---    Thanks for replying Rodo, but I don't understand your question very well, maybe I should try to explain clearly. The two clock inputs generated by PLL are used to drive the internal logic of "customized subsystem" (they are basically FIFO queues) that is in charge of exchanging data between the FPGA and the ADC and DAC boards. The problem is that I have to use the same clock signals for both the internal logic and the ADC-DAC clocks. That is the reason why "customized subsystem" has two clock inputs and two conduit inputs. In this case, conduits inputs are used only to conduct same clock signals through two FPGA pins connected to ADC-DAC clocks pins. To sum up, Qsys doesn't allow me to connect Altera PLL outputs to customized subsystem clocks inputs and conduits inputs simultaneously.   One solution to sove this problem consists on instantiate the Altera PLL in the top system, and inyect clock signals of customized subsystem through "clock bridges" core, and also inyects the same signals through conduits input (exported previously in Qsys ). However, if possible I would like to instantiate PLL inside Qsys design.