Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16608 Discussions

Ability to quickly integrate IPs in OpenCL

Altera_Forum
Honored Contributor II
‎03-13-2016 04:58 PM
1,184 Views

hello, 

 

I'm MESSELKA Mohamed Student at University Polytechnic of Valencia, I'm working on my final project and I need a document about ''Ability to quickly integrate IPs in OpenCL'' to insert a Verilog Code in OpenCL, so please I need your help to write my memory and I hope you will contact me as soon as possible, my email: m14m@live.fr. 

see the attached photo will give a clear idea about my question. 

 

 

thank you in advance. 

 

 

kind regards 

MESSELKA Mohamed
Preview file
21 KB
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎03-14-2016 08:36 AM
472 Views

As far as I know this is not possible, you'll need to adapt the BSP as well, but, maybe, you can change the generated Verilog to your specifications. I have no idea if this will work but that's what I would try.  

 

Again, as far as I know this is not the correct way of doing things.
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎03-14-2016 08:42 AM
472 Views

Just read this thread:http://www.alteraforum.com/forum/showthread.php?t=51699 

Tricky says about the same.
0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.