Seriallite II C2C Issue

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Seriallite II C2C Issue

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Hi,

I'm working on setting up the seriallite II ip to send data collected on one FPGA to another on the arria v dual FPGA development board. I have a transmitting seriallite core on one FPGA and a receiving one on the other, they are sending and receiving data in streaming mode. The transmitting core seems to be working correctly, however the receiving core doesn't lock onto the incoming data (rx_is_lockedtoref does not get asserted). Any idea why this lock is not being established? I've attached some waveforms and rtl viewer screenshots to this message.

Regards,

Arash

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