Cyclone V clock output pins

[Altera_Forum]

On the Cyclone V C3 device there are pins called FPLL_BL_CLKOUT0 and FPLL_BL_CLKOUT1 and similar pins on the other side FPLL_BR_CLKOUT0 and FPLL_BR_CLKOUT1. The implication is that they are specialist pins which can be driven as a clock output by an fPLL. 

 I can't find anything in the C V Device Handbook about which of the fPLLs are supposed to drive these pins, so I did a little test. I provide a 100 MHz clock input on one of the global clock input pins. I instantiated an ALTPLL which has four outputs: two at 100 MHz, two at 125 MHz. One of each frequency drives an output pin directly, and the other of each frequency clocks a toggle flip-flop whose Q output drives a pin.  In the pin planner, I assigned the 100 MHz clock input to a global clock input. I purposely did not make any assignments for the other pins. I ran the design through Quartus 15.1, and it was perfectly happy. I checked the resulting pin-out file to see what pins Quartus used for the clock outputs, and they turned out to be just general-purpose I/O pins, not the specialist pins noted above.   Next, I assigned the clock outputs to the specialist pins, ran the tools, and again they were happy.  One thing I noticed was that in both cases, Quartus consolidated the two pairs of PLL outputs into just two outputs, one for the 125 MHz clock and the other for the 100 MHz clock.   It appears that, at least in the C V devices, one can drive both an output pin and internal logic clock inputs off of a PLL output.  What, then, is the point of the specialist FPLL_BL_CLKOUT0 pins? I can't find anything in the handbook that specifically mentions why they'd be used.

[Altera_Forum]

I don't think Quartus automatically routes to specialized clock pins. In any case, any I/O pin should be fine with 100 MHz.

[Altera_Forum]

The PLL clock output pins have dedicated, fast routing, so that the delay to these pins is minimised or, perhaps more importantly, known. 

 Using ordinary I/O will result in Quartus using up ordinary routing resources, whose delay will change each time you run your design through Quartus. So, depending on your board design, and what this output clock is used for, you may end up with a working board one minute and a non-working board the next courtesy of a new FPGA build, even though you may not have changed anything to do with the output clock in your FPGA design.  Cheers, Alex

[Altera_Forum]

--- Quote Start ---  The PLL clock output pins have dedicated, fast routing, so that the delay to these pins is minimised or, perhaps more importantly, known.  --- Quote End ---    thank you -- this is what I was hoping that the documentation would say.

[Altera_Forum]

I have a similar question to this. I'm designing a DDR3 interface in a Cyclone V 5CEBA5 F484 device. I'm using bank 4A as the interface because it has 48 pins of which I'm using 40. There are no PLL clock out pins in this bank so I've allocated 2 CLKIN pins, CLK2p and CLK2n for my DDR_CLK and DDR_CLK_N outputs. The fitter hasn't 'complained' so my question is are these clock outputs being treated as ordinary I/O whose delay will change each time it's run through Quartus? 

 Thanks, Clive

[Altera_Forum]

--- Quote Start ---  I have a similar question to this. I'm designing a DDR3 interface in a Cyclone V 5CEBA5 F484 device. I'm using bank 4A as the interface because it has 48 pins of which I'm using 40. There are no PLL clock out pins in this bank so I've allocated 2 CLKIN pins, CLK2p and CLK2n for my DDR_CLK and DDR_CLK_N outputs. The fitter hasn't 'complained' so my question is are these clock outputs being treated as ordinary I/O whose delay will change each time it's run through Quartus?  Thanks, Clive  --- Quote End ---    Think I've found an answer. The External Memory Interface Handbook Vol 2 states in section 1.1.2 "you should generate the CK and CK# signals using the DDR registers in the IOE to match with the DQS signal ". I'm using the DDR3 SDRAM Controller with UniPHY MegaCore so presumably this will do it all for me :)?   Could someone please confirm this for me?