Gate Level Simulation Error

[Altera_Forum]

Hi all, I have written some code for a basic and gate with a test bench, which works just fine when I run it in the RTL simulation, however whenever I try and run it in the Gate Level simulation I keep getting these error: 

  Loading work.tb_and_4bit# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".# No such file or directory. (errno = ENOENT)# Loading work.and_4bit# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".# No such file or directory. (errno = ENOENT)# ** Error: (vsim-3033) 4bit_ALU_7_1200mv_0c_slow.vo(74): Instantiation of 'cycloneive_io_obuf' failed. The design unit was not found.# Region: /tb_and_4bit/DUT# Searched libraries:# c:\altera\90\modelsim_ase\altera\verilog\altera# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".# No such file or directory. (errno = ENOENT)# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".# No such file or directory. (errno = ENOENT)# ** Error: (vsim-3033) 4bit_ALU_7_1200mv_0c_slow.vo(84): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found.# Region: /tb_and_4bit/DUT# Searched libraries:# c:\altera\90\modelsim_ase\altera\verilog\altera# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".# No such file or directory. (errno = ENOENT)# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".# No such file or directory. (errno = ENOENT)# ** Error: (vsim-3033) 4bit_ALU_7_1200mv_0c_slow.vo(94): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found.# Region: /tb_and_4bit/DUT# Searched libraries:# c:\altera\90\modelsim_ase\altera\verilog\altera# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".# No such file or directory. (errno = ENOENT)# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".# No such file or directory. (errno = ENOENT)# ** Error: (vsim-3033) 4bit_ALU_7_1200mv_0c_slow.vo(111): Instantiation of 'cycloneive_lcell_comb' failed. The design unit was not found.# Region: /tb_and_4bit/DUT# Searched libraries:# c:\altera\90\modelsim_ase\altera\verilog\altera# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".# No such file or directory. (errno = ENOENT)# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work# Error loading design  I have the cyclone_iv library's downloaded and installed.  Many thanks.

[Altera_Forum]

Is gate level simulation even available in the free version of Quartus/Modelsim?