Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Infering dual port ROM

Altera_Forum
Honored Contributor II
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Hello; 

I'd like to get a VHDL code to infere a dual port ROM but with a registered address. 

Thanks
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Altera_Forum
Honored Contributor II
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It always pays to Read the manual: 

 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts_qii5v1.pdf 

 

section 12 (specially page 12-27 - Inferring ROM Functions from HDL Code)
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

It always pays to Read the manual: 

 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts_qii5v1.pdf 

 

section 12 (specially page 12-27 - Inferring ROM Functions from HDL Code) 

--- Quote End ---  

 

 

Thanks for your attention. I refereed to this section. But it has a registered output dual ROM. I want a registered address dual ROM.
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Altera_Forum
Honored Contributor II
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What exactly do you mean by "registered address" rom? All internal memory elements require a registered read address in order to infer the code into memory blocks, otherwise it will infer a LUTram.

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Altera_Forum
Honored Contributor II
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Thanks M.Tricky for ur attension. 

I mean a "registered read address" dual ROM, Is there a VHDL code to infer it?
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Altera_Forum
Honored Contributor II
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Why not just register the read address before reading from ROM? 

It doesnt need a specific code example, just put together a register and a ROM.
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Altera_Forum
Honored Contributor II
427 Views

OK; 

These ROMs are part of pipeline, I tried to infer an asynchronous read address and read data ROM but I failed. It is ok if there is a code to infer a non registered read address or read data ROMs.
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Altera_Forum
Honored Contributor II
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Asynchronous read address rams (ie. read address not registered) can only be inferred using LUTRAM.

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