Synthesize multipliers on distributed logic?

[Altera_Forum]

Hello, 

I want to synthesize a symmetric FIR filter with 116 taps. Thus, the design should infer 58 multipliers. As I start the design flow for a Cyclone V (5CSEMA4U23C6) with 84 DSP blocks, everything works as expected. If I change the target device to a smaller FPGA (5CEFA2F23C8N), the tool reports that the design uses too much DSP blocks but only 25 DSP blocks are available. That's ok, I totally agree and conclude, that the tool cannot synthesize the arithmetic on the distributed logic. But, if I select the 5CSEBA2U19C8 with 36 DSP Blocks, nothing behaves as expected. The tool reports a correct usage of 58 DSP blocks (analysis and synthesis). Further, the fitter reports a usage of 36 DSP blocks and a total number of 58 fixed point multipliers. Consequently, that means that 22 multipliers are built on distributed logic. The logic utilization is 1437/9430 ALM (15%). Why can the tool not implement the design on the 5CEFA2F23C8N (which also includes 9430 ALMs)?  I'm new to the Altera world. This exercise is for evaluation. I'm using Quartus Prime Lite 15.1  Thank you.

[Altera_Forum]

--- Quote Start ---   But, if I select the 5CSEBA2U19C8 with 36 DSP Blocks, nothing behaves as expected. The tool reports a correct usage of 58 DSP blocks (analysis and synthesis). Further, the fitter reports a usage of 36 DSP blocks and a total number of 58 fixed point multipliers. Consequently, that means that 22 multipliers are built on distributed logic. The logic utilization is 1437/9430 ALM (15%).  --- Quote End ---    I guess that the multiplications fit into an 18 x 18 multiplier, and Quartus can construct up to 72 of those out of the 36 available DSP blocks.

[Altera_Forum]

Yes, the multiplication fits into 18x18 multiplier. I already figured out that a DSP block contains two 18x19 multipliers... 

But does it also mean, that a multiplier cannot be synthesized to the distributed logic?

[Altera_Forum]

--- Quote Start ---  But does it also mean, that a multiplier cannot be synthesized to the distributed logic?  --- Quote End ---   In Assignments->Settings->Compiler Settings->Advanced Settings (Synthesis) you can set dsp block balancing to logic elements, but then it will only infer LEs. You may want to experiment with these settings.

[Altera_Forum]

Ok. I will play around with the options. Thank you for your comments.

[Altera_Forum]

you can individually control each multiplier using the multstyle synthesis attribute: 

 http://quartushelp.altera.com/14.0/mergedprojects/hdl/vhdl/vhdl_file_dir_multstyle.htm

[Altera_Forum]

My little exercise is completed. The symmetric 116 tap FIR filter (18 bit coefficients) fits into the small Cyclone V FPGA with 25 DSP blocks. That means, the tool can even place the multipliers on distributed logic. This can be achieved by the multstyle synthesis attribute. Thanks for the help.