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Automated Verilog Module Instantiation

Altera_Forum
Honored Contributor II
‎04-26-2016 03:44 AM
1,821 Views

A python implementation of automated verilog module instantiation. 

 

https://aprogrammersparadise.wordpress.com/2016/04/26/automated-verilog-module-instantiation/
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Altera_Forum
Honored Contributor II
‎04-26-2016 04:48 AM
711 Views

Hello, 

 

Although I do not have knowledge about Python, it is very good that you put your good efforts and got success in that. I really appreciate work you have done to make Verilog Programmers' life easier. 

 

I request you to have a look at http://www.veripool.org/wiki/verilog-mode. 

 

By using /*AUTOINST*/ keyword in Verilog-mode, you can do same thing which you have done. ( Help on this is available at : http://www.veripool.org/projects/verilog-mode/wiki/verilog-mode-help ) 

 

Have a Great Day! 

 

Cheers, 

Bhaumik
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