- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I'd like to export the Altera Avalon-MM SDRAM controller from QSYS on my BEMICRO MAX10 FPGA eval board.
I won't be using NIOS-II, but my own (and open-source) custom verilog hardware. The plan is to attach the SDRAM controller to a soft-core CPU called the J68, which is a Motorola 68000 cpu. Previously, I have successfully connected the User Flash Memory using the on-chip flash IP. It's also through QSYS, but doesn't seem to require an SOPC/system/other configuration. It looks like I have to fake a clock and reset inside QSYS, just to remove the errors, so that I can properly export the SDRAM controller. Any other suggestions, helpful hints, or make-sure-to-dos when dealing with the controller in this fashion? Thanks Keith- Tags:
- qsys
Link Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi, I see none answered your question, I read three times and I never understood what you wish to do nor on which trouble you get stuck at.
Can you be more precise on what is your goal and what help you need? Best regards
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page