Debugging FPGA Timer on AXI bus generates RESET EXCEPTION

[Altera_Forum]

I’m starting this thread because I haven’t been able to find anyone else who is having this problem. I’m working with two boards: the DE1-SOC eval board and a custom board that uses a Cyclone V 5CSEBA2 device. I’m working with one of the ARMs in the device and I’m trying to control/communicate devices implemented in the FPGA fabric that are slaves on the LW AXI bus. This is a bare metal project. 

So far I have two custom modules each with a few control registers plus a system ID register. I have also created a timer slave for the LW AXI bus and I’m using it to generate interrupts at the rate I expect my data processing module to generate interrupts. I’m doing this so I can get the interrupts working without having to worry about the complexity of the data processing module. The interrupt handler accesses a few registers in the timer and sets a software flag (I’m not doing any print statements). When I step through the code with the DS-5 debugger everything works. However if I just let the program run without setting break point a reset exception is generated. As an experiment I’m also using one of the ARM timers to generate the interrupt but I still bang all the registers in my AXI bus modules during the ISR and it works fine – all the register are written with the correct values and the system doesn’t generate any exceptions. I’ve also experimented with just polling the AXI bus timer instead of using interrupts and I get the reset exception. This happens on both my eval board and my custom board. I originally tried this exercise using Altera’s Avalon timer and got the same reset exception behavior. I’m using the altera-socfpga-hardwarelib-timer-cv-gnu-debug example program provided with the DS-5 tools as the go-by for setting up the GIC and for the interrupt handler. I’ve verified that my AXI interface is not violating any specs (I’ve also used this interface module in several Zynq projects without any issues). Any help would be appreciated.