Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Quartus Prime 16.0.0 warning 332056 PLL cross checking issue

Altera_Forum
Honored Contributor II
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Placing a PLL with no phase shift is causing this warning when Fitting is running : -phase (expected 4.50, found 0.00) 

 

I set the generated clock constraint "-phase" to 0 in the sdc. 

 

If I derive the PLL generated clock from TimeQuest it sets the -phase 4.5 and the warning is no more although what I am worried about is that the sdc isn't representing the real configuration then! 

 

Any idea why the tool expects 4.5 degrees when my PLL IP configuration clock phase is 0? 

 

Also, when I apply a phase shift to the PLL, the number generated by TimeQuest for the constraint is different, usually much smaller! 

 

Note this warning happens with v16.0.0 and not in Quartus2 13.1
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