TSW1400EVM / Altera Stratix IV / PLL replacement

[Altera_Forum]

Hello, 

  I have purchased the TSW 1400 EVM containing a Altera Stratix IV FPGA and my objective is to use simultaneously the ADC and DAC interface.   I have analysed both firmware's used by TI for the ADC and DAC and i can successfully use both separately. However, when i try to put both codes together it's not possible to fit the design in the Altera Software Quartus because the ADC interface uses 3 PLL and the DAC 4, but the TSW1400EVM only has 4 PLL in total.   I would like to ask if someone can give me a direction to interface both ADC and DAC simultaneously, or a way to replace a PLL it's get possible to fit the design.       Any help would be great appreciated,   Regards.

[Altera_Forum]

Not possible to help you without detailed knowledge of that EVM and the ADC and DAC FPGA designs. You may get lucky and someone here who has used that kit will chime in, but if that doesn't happen have you considered asking TI for help? If they provided the FPGA code then that may be a better way to go. In my experience TI's technical support has always been very good. Could be a long wait for answers here, and since this is not an Altera product I'm not sure you could get much support from Altera.

[Altera_Forum]

--- Quote Start ---  Not possible to help you without detailed knowledge of that EVM and the ADC and DAC FPGA designs. You may get lucky and someone here who has used that kit will chime in, but if that doesn't happen have you considered asking TI for help? If they provided the FPGA code then that may be a better way to go. In my experience TI's technical support has always been very good. Could be a long wait for answers here, and since this is not an Altera product I'm not sure you could get much support from Altera.  --- Quote End ---    I understand that anyone without detailed knowledge probably won't be able to help me, but as you said, maybe i get lucky to find someone that has worked before with that board.  I also asked helped for T.I., i'm trying all the possible ways to solve it, but through my research and their feedback, what i'am attempting to do has never been tried. My intention on asking Altera's help is to find a direction on how to replace, if possible, a PLL in the Altera stratix IV FPGA. Thanks for your advices and time.

[Altera_Forum]

Follow up with an inventory of what ADC, DAC you're using and in what mode[s] you would like to operate them. 

Then also describe how the (7) PLL are being used (what clock input, output they generate). Then, you may get some feedback on some simple modification to combine PLL's based on how they overlap.

[Altera_Forum]

--- Quote Start ---  I understand that anyone without detailed knowledge probably won't be able to help me, but as you said, maybe i get lucky to find someone that has worked before with that board.  I also asked helped for T.I., i'm trying all the possible ways to solve it, but through my research and their feedback, what i'am attempting to do has never been tried. My intention on asking Altera's help is to find a direction on how to replace, if possible, a PLL in the Altera stratix IV FPGA. Thanks for your advices and time.  --- Quote End ---    I'm guessing that with ADCs and DACs the designs are using LVDS serdes, which are usually built with the PLLs internal to the IP (which is just a logical partition, the PLLs are separate on the chip). If that's what's going on then you could rebuild the LVDS serdes IP cores to use an external PLL, then you may be able to share PLLs between the ADC (LVDS Rx) and DAC (LVDS Tx) interfaces. But it will most likely be on you to dig in, do the research, and make the changes.  As ted said, post back here with specific questions after you dive into the designs a little deeper.  Bob

[Altera_Forum]

Hi, 

I am running into some issues with PLL on this board too. Here is what I am trying to do 1. If I implement left/right pll (altpll) function by itself with clk8p input, it detects and implements it as PLL_R2. I can write my own code for deserialization and I don't get any errors and the project compiles with no errors and I can do testing 2. Once I add altrvds_rx to the design (I would like to use the channel data alignment and lvds_clk rising edge options) and feed the clocks from the same left/right PLL, I can't even compile the code and fitter gives warnings a.can't place left/right pll in target device due to device constraints b.can't place in pll location pll_b1, because it doesn't accept left/right plls c.can't place in pll location pll_r2 due to device constraints (it was implemented in this location before adding altlvds_rx) d.can't place in pll location pll_t1 because the location doesn't accept left/right plls e.can't place in pll location pll_l2 because pll has a location assignment that is incompatible  when I look at the documentation for clock network in stratix IV GX 70, 1152 pin external memory interfaces clk8p,9p,10p,11p left/right pll is pll_r2, which unfortunately is giving errors after adding altlvds_rx block the settings I am using are similar to the source code provided by TI for this board. TI's code compiles with no errors and shows the right location assignments. If someone has come across something similar, please let me know  Thanks, Ramakrishna