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Hi,
I am trying to use VHDL-2008 in Quartus Prime 16.0.0 I have a package with declaration of unconstrained array of unconstrained records type:
type packet_uinstr_t is record
src_col : std_logic_vector; --! address to GMII buffer, src_row is implicit (position in the signal itself) (MSB in MVB)
dst_row : std_logic_vector; --! address to PCIE buffer
dst_col : std_logic_vector; --! address to PCIE buffer
barrier_flag : std_logic_vector; --! barrier flag, probably just std_logic (LSB in MVB)
end record;
Then I have entity with this type:
RX_PACKET_UINSTRS : in packet_uinstrs_t(0 to INPUT_ROWS-1)(src_col(log2(INPUT_COLS)-1 downto 0),
dst_row(log2(OUTPUT_ROWS)-1 downto 0), dst_col(log2(OUTPUT_COLS)-1 downto 0),
barrier_flag(BARRIER_WIDTH-1 downto 0));
In synthesis I get this error: Error (10410): VHDL Type Conversion error at planner_ent.vhd(80): Type Conversion near text or symbol "packet_uinstr_t" must have one argument I already specified VHDL-2008 in "Compiler Setting/VHDL Input" and in Files/Properties/HDL version for each file. Question: Is this construct supported in Quartus Prime? This very same code is perfectly fine with Modelsim. Thanks for any info... [SOLVED] in Quartus Prime PRO 16.0 it's perfectly working...
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4 Replies
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Quartus Support for VHDL 2008 is rather limited and far from full. Reading in the help, http://quartushelp.altera.com/current/#hdl/vhdl/vhdl_list_2008_vhdl_support.htm, Quartus supports unconstrained arrays, but it doesnt specify unconstrained records.
I suggest filing an enhancement request via Mysupport.- Mark as New
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Is this feature finally supported in Quartus 18.0 ?
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Quartus Prime Pro has had full 2008 support since v16 or 17.
Prime standard has a limited subset of 2008 feature support. Unconstrained records is not one of them.
Prime standard is pretty much ignored now by the devs.
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@Tricky Thank you for your reply. Currently I work with Cyclone V and unfortunately, according to my understanding, Quartus Pro doesn't support it.
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